Synchronous Semiconductor Memory Latency Counter Design
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Solution Overview
Problem
Conventional synchronous semiconductor memory devices experience a rapid increase in consumption current as external clock speed increases, limiting operation timing margins and requiring a wide range of latency counting capabilities.
Innovation Solution
A synchronous semiconductor memory device utilizing internal clocks with a 180-degree phase difference to selectively set and count various latencies, employing two counter circuits to manage even and odd number latencies, reducing consumption current and enhancing operation timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the external clock speed is increased to achieve higher operation speed, then the productivity is improved, but the consumption current increases rapidly
Solution Approach 1:
The latency counter is divided into a first counter circuit for counting even-number clock cycles and a second counter circuit for counting odd-number clock cycles. This segmentation allows the use of internal clocks running at half the external clock frequency, thereby reducing consumption current while maintaining the ability to count the full range of latency values.
Solution Approach 2:
The patent changes the operating frequency parameter of the counter circuits by using internal clocks with half the frequency of the external clock. This parameter change reduces the dynamic power consumption (which is proportional to frequency) while still achieving the required latency counting function through the dual-circuit architecture.
2Productivity
If the external clock speed is increased to achieve higher operation speed, then the productivity is improved, but the operation timing margin decreases
Solution Approach 1:
By segmenting the latency counter into two separate counter circuits that each operate at half the external clock frequency, the patent creates more relaxed timing requirements. Each counter circuit has sufficient time to complete its counting operation within the available clock cycle, thereby maintaining operation timing margin even at high external clock speeds.
3Device complexity
If a single counter circuit is used to count all latencies, then the device complexity is reduced, but the adaptability to count both even and odd latencies is limited
Solution Approach 1:
The latency counter is segmented into two specialized counter circuits: one for even-number latencies and one for odd-number latencies. This segmentation provides the adaptability to accurately count any latency value while keeping each individual counter circuit relatively simple in structure.
Solution Approach 2:
The dual counter circuit architecture provides universal latency counting capability, handling both even and odd latency values through a unified structure. The control logic selectively activates the appropriate counter circuit based on the desired latency value, achieving multi-functionality without requiring completely separate counting paths.
Data Source
AI summary
A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.