Memory Device Latency Circuits with FIFO and Wave Pipeline
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Solution Overview
Problem
Conventional synchronous memory devices face challenges in accommodating varying data access latencies, requiring complex control circuits and simulations for shorter latencies, and are difficult to modify for larger latency changes without incurring speed penalties.
Innovation Solution
The implementation of memory devices with latency circuits that include first-in-first-out (FIFO) circuits and wave pipelines, allowing for programmable latency options by controlling the clocking of data into and out of FIFOs, and enabling asynchronous operation of wave pipeline sections independent of periodic clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional control circuits are designed to accommodate shorter latencies, then read/write latency is reduced, but device complexity increases and the circuits cannot accommodate larger latencies
Solution Approach 1:
The patent implements dynamic latency adjustment by making the memory device adaptable to different latency requirements through programmable configuration. The control circuits can be programmed to support multiple latency values, allowing the system to dynamically adjust timing parameters based on operational needs rather than being fixed to a single latency value.
Solution Approach 2:
The patent changes the timing parameters of the memory device by allowing programmable latency values. By modifying the latency parameter through programming, the device can accommodate different read/write timing requirements without hardware redesign, thus reducing complexity while maintaining flexibility.
2Manufacturing precision
If clocked pipeline read path is designed with equal delay sections, then timing precision is improved, but adaptability to change latency decreases and speed penalty occurs
Solution Approach 1:
The patent introduces dynamic latency adjustment capability to the clocked pipeline read path. By making the latency programmable, the system can adapt to different timing requirements without being constrained by fixed equal delay sections, thus improving adaptability while maintaining timing precision through controlled programming.
Solution Approach 2:
The patent creates a universal read path design that can function with multiple latency values. The programmable control circuits enable the same hardware structure to serve multiple timing requirements, eliminating the need for separate designs for different latency values and avoiding speed penalties.
3Productivity
If memory device operates at higher speed, then productivity is improved, but ability to accommodate larger latencies is reduced
Solution Approach 1:
The patent implements dynamic latency configuration that allows the memory device to operate at high speeds while maintaining the capability to accommodate larger latencies when needed. The programmable control circuits enable the system to switch between different latency modes without sacrificing operating speed, thus resolving the trade-off between productivity and adaptability.
Data Source
AI summary
A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed.