Memory Access Latency Control for SoC Thermal Mitigation
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Solution Overview
Problem
High-performance integrated circuits, such as SoCs, generate excessive heat due to high switching activity and density, leading to overheating issues that are difficult to manage in compact form factors, and existing thermal mitigation methods like reducing frequency and putting components into idle states compromise performance.
Innovation Solution
Implementing a thermal monitor and memory controller system that delays memory access in response to thermal states, reducing switching frequency without altering clock frequencies or voltages, using tunable delay elements to manage heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the clock frequency is reduced to mitigate thermal issues, then the temperature is reduced, but the performance of the integrated circuit is reduced
Solution Approach 1:
The patent segments the clock signal distribution by introducing separate delayed and non-delayed clock paths. Different functional units receive clock signals with different delays, allowing selective thermal mitigation in specific segments without affecting the entire processor's performance. This enables localized frequency control where only overheating units receive delayed clock signals.
Solution Approach 2:
The patent implements dynamic clock frequency adjustment based on real-time temperature monitoring. The system continuously monitors temperatures of functional units and dynamically adjusts the clock signal delay for each unit accordingly. This dynamic adaptation allows the system to maintain high performance when cool and apply thermal mitigation only when and where needed.
2Temperature
If components are put into idle or sleep states to reduce switching activity, then heat generation is reduced, but the performance is reduced
Solution Approach 1:
The patent changes the timing parameter of clock signals rather than putting components into idle or sleep states. By adjusting the phase and delay of clock signals delivered to functional units, the system reduces switching activity and heat generation while keeping components in an active state, thus maintaining performance readiness without the performance penalty of idle/sleep transitions.
3Temperature
If the switching frequency is reduced to mitigate thermal issues, then the temperature is reduced, but the performance is reduced
Solution Approach 1:
The patent segments the clock signal distribution by introducing separate delayed and non-delayed clock paths. Different functional units receive clock signals with different delays, allowing selective thermal mitigation in specific segments without affecting the entire processor's performance. This enables localized frequency control where only overheating units receive delayed clock signals.
Solution Approach 2:
The patent implements dynamic clock frequency adjustment based on real-time temperature monitoring. The system continuously monitors temperatures of functional units and dynamically adjusts the clock signal delay for each unit accordingly. This dynamic adaptation allows the system to maintain high performance when cool and apply thermal mitigation only when and where needed.
4Temperature
If additional cooling systems are added to manage heat, then thermal issues are mitigated, but the device complexity increases
Solution Approach 1:
The patent implements a self-regulating thermal mitigation system that uses existing processor components (temperature sensors, clock distribution network) to automatically control heat generation. The system monitors its own temperature and self-adjusts clock signal delays without requiring external cooling control systems, thereby managing thermal issues while avoiding additional system complexity.
Data Source
AI summary
Aspects relate to using memory access latency to mitigate thermal excesses in a System on a Chip (SOC). An apparatus includes a processing core, a memory, and thermal monitor configured to determine a thermal state of the processing core. A memory controller is coupled to the processing core, to the thermal monitor, and to the memory, and configured to provide the processing core with access to the memory, the memory controller further configured to delay access to the memory in response to the thermal state.