Memory Device Lateral Offset Stack Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits shrink, existing memory devices face challenges in achieving higher storage capacity and lower costs per bit while maintaining efficient operation and reducing RC delay.
Innovation Solution
A memory device with a stack structure comprising a source layer, insulating layer, and gate electrode layers, where memory cells are defined between the channel element and gate electrode layers, and a semiconductor layer is electrically connected between the source and channel elements, featuring a unique semiconductor layer composition with lateral offsets and different conductivity types to reduce resistance and eliminate PN junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If critical dimensions are shrunk to increase storage capacity, then storage capacity increases, but RC delay increases and manufacturing precision becomes more difficult
Solution Approach 1:
The patent transitions from planar 2D memory structures to three-dimensional vertical stack structures with multiple gate electrode layers stacked vertically. This dimensional change allows increased storage capacity without proportionally shrinking lateral critical dimensions, thereby avoiding the associated manufacturing precision challenges and RC delay penalties.
Solution Approach 2:
The patent implements nested semiconductor layers within vertical stack structures, where multiple semiconductor layers are positioned at different vertical levels between source and channel elements. This nesting approach increases storage capacity while maintaining larger lateral dimensions that are easier to manufacture with existing precision capabilities.
2Quantity of substance
If critical dimensions are shrunk to increase storage capacity, then storage capacity increases, but RC delay increases
Solution Approach 1:
By moving to vertical 3D stacking, the patent increases storage capacity without proportionally reducing lateral dimension sizes. This maintains shorter lateral current paths and reduces RC delay while achieving higher density through vertical layering.
Solution Approach 2:
The patent divides the semiconductor structure into multiple segmented layers with different conductivity types (n-type and p-type) arranged vertically. This segmentation creates multiple parallel conduction paths that reduce overall resistance and mitigate RC delay while increasing storage capacity.
Data Source
AI summary
A memory device includes a stack structure, a memory element, a channel element, and a semiconductor layer. The stack structure includes a source layer, an insulating layer and gate electrode layers. The insulating layer is on the source layer. The gate electrode layers are on the insulating layer. The memory element is on electrode sidewall surfaces of the gate electrode layers. Memory cells are defined in the memory element between the channel element and the gate electrode layers. The semiconductor layer is electrically connected between the source layer and the channel element. The semiconductor layer and the source layer have an interface therebetween. The interface is at a location on an inside of an insulating sidewall surface of the insulating layer with a lateral offset relative to the insulating sidewall surface.