Memory Lattice Address Decoders for Efficient Machine Learning Inference
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Solution Overview
Problem
Current machine learning techniques are memory-hungry, energy-intensive, and time-consuming, particularly during training, and are prone to over-fitting, making them inefficient for real-time applications and requiring large-scale computing machinery, which limits their use in everyday devices and robustness against noisy data.
Innovation Solution
A memory access method using a memory lattice with address decoder elements that perform subsampling and coincidence-based activation, allowing for efficient feature extraction and inference by storing class information at memory locations identified by feature coincidences, enabling one-shot learning and reducing training time and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional machine learning techniques are used for training and inference, then processing capability is improved, but memory consumption increases significantly and energy consumption increases
Solution Approach 1:
The patent segments the machine learning model into distinct components: address decoder elements that subsample input data and generate activation signals, and memory storage locations that store class information. This segmentation allows the system to process data in a distributed manner across multiple memory devices, reducing the memory burden on any single device while maintaining overall processing capability.
Solution Approach 2:
The patent introduces a coincidence detection dimension by requiring simultaneous activation of multiple address decoder elements (e.g., row decoder and column decoder) to access a memory location. This dimensional approach transforms the memory access pattern from traditional sequential addressing to a parallel coincidence-based model, enabling efficient feature extraction with reduced memory requirements.
2Measurement precision
If conventional machine learning training is performed, then model accuracy is improved, but training time increases significantly and energy consumption increases
Solution Approach 1:
The patent performs preliminary subsampling and feature extraction at the address decoder element level before memory access. By pre-processing input data to generate activation signals that directly map to memory locations, the system eliminates the need for time-consuming sequential processing during training and inference, significantly reducing training time while preserving model accuracy.
Solution Approach 2:
The patent replaces traditional mechanical/sequential processing mechanisms with a coincidence-based activation system. Instead of sequentially processing data through multiple layers, the system uses parallel coincidence detection across address decoder elements, substituting time-intensive sequential operations with simultaneous parallel operations that achieve the same computational goal faster.
3Ease of operation
If traditional memory addressing is used, then data access is straightforward, but processing speed for high volume data decreases
Solution Approach 1:
The patent merges multiple address decoding functions into a unified coincidence-based access mechanism. By combining row and column address decoders that operate simultaneously on the same input data, the system achieves parallel data access across multiple memory locations, dramatically increasing processing speed for high-volume data while maintaining operational simplicity through standardized memory access interfaces.
4Productivity
If conventional machine learning models are deployed, then processing power is improved, but device complexity increases and requires large-scale computing machinery
Solution Approach 1:
The patent creates a universal memory-based processing architecture where address decoder elements can subsample various types of input data (images, audio, sensor data) and the same memory storage structure handles different classification tasks. This multi-functional design enables the system to achieve high processing power for diverse applications without increasing device complexity, as the same hardware components serve multiple purposes.
5Adaptability or versatility
If standard memory access methods are used, then compatibility is maintained, but energy consumption during inference increases
Solution Approach 1:
The patent extracts only the essential class information from training data and stores it in memory, eliminating the need to store and process entire training datasets during inference. By extracting and storing only the critical coincidence patterns and class labels, the system maintains compatibility with standard memory interfaces while dramatically reducing energy consumption during inference operations.
Data Source
AI summary
A computer memory apparatus is provided having a plurality of storage locations and a plurality of address decoder elements, each having a one or more input address connections for mapping to a respective one or more data elements of an input data entity. Decoding by a given one of the plurality of address decoder elements serves to conditionally activate the address decoder element depending on a function of values of the one or more data elements of the input data entity mapped to the one or more input address connection(s) and further depending on an activation threshold. Memory access operations to one of the plurality of storage locations are controlled by two or more distinct ones of the plurality of address decoder elements depending on coincidences in activation of the two or more distinct address decoder elements as a result of the decoding. A method and machine-readable instructions are also provided.