3D Memory Layer Structure for Buckling-Resistant Fabrication

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor memory devices face issues with structural defects such as deflection and buckling of insulating layers during the manufacturing process, leading to embedding failures and reduced manufacturing yield, especially in multi-layer structures with varying stress concentrations.

Innovation Solution

The use of alternating layers of sacrifice layers made of different materials, such as polycrystalline silicon and silicon nitride, with specific etching solutions to selectively remove these layers, ensuring structural support and reducing stress-induced defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-layer structures are used to increase storage capacity, then storage capacity is improved, but structural defects such as deflection and buckling of insulating layers occur

Engineering Contradiction:
Improvestorage capacityVSAvoidstructural integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the multi-layer structure into alternating layers of first insulating layers and second insulating layers with different stress characteristics. This segmentation allows each layer type to compensate for stress in specific regions, preventing overall structural failure while maintaining high storage capacity through the multi-layer configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different material properties to different layers: first insulating layers with first stress characteristics and second insulating layers with second stress characteristics. This local differentiation of material qualities enables targeted stress management in different regions of the multi-layer structure, preventing deflection and buckling while maintaining structural integrity.

Inventive Principle:
Principle #3Local quality

2Productivity

If alternating layers of different materials are used to reduce stress defects, then manufacturing yield is improved, but device complexity increases

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidlayer structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and removes sacrifice layers from the structure after they have served their stress-compensation function during manufacturing. This removal eliminates the need to permanently incorporate complex multi-material structures into the final device, thereby improving manufacturing yield through better stress management while reducing the complexity of the final product structure.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent utilizes parameter changes in material stress characteristics between different insulating layer types. By carefully selecting materials with complementary stress properties and controlling their thickness parameters, the patent achieves stress balance that improves manufacturing yield without requiring excessive structural complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances manufacturing yield by minimizing structural defects, allowing for the formation of multi-layer memory cell arrays with increased storage capacity and reliability.

Implementation Method 1

The use of alternating layers of sacrifice layers made of different materials, such as polycrystalline silicon and silicon nitride, with specific etching solutions to selectively remove these layers

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS20260068156A1Semiconductor memory device and manufacturing method thereof
Publication Date: 2026.03.05 KIOXIA CORP
  • US20260068156A1 patent drawing
  • US20260068156A1 patent drawing
  • US20260068156A1 patent drawing

AI summary

A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.