Memory Layer Etching for Capacitor Coupling Without Bitline Shorts
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Solution Overview
Problem
Substrate processing systems face challenges in detecting partial unclamping of substrates from electrostatic chucks during etching processes, which can lead to electrical shorts and damage to memory structures due to uneven etching of dielectric layers and active silicon regions.
Innovation Solution
A substrate processing system with a system controller that performs controlled deposition and etch cycles, including breakthrough and over-etch operations, to selectively etch active silicon regions while minimizing dielectric layer etching, using specific gas mixtures and RF signal applications to ensure precise exposure and access for capacitor coupling, and filling trenches with conductive material to prevent shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to access active silicon regions, then dielectric layers are removed, but electrical shorts occur due to uneven etching and damage to memory structures
Solution Approach 1:
The etching process is divided into multiple sequential steps: first etching dielectric layers to expose the upper portion of active silicon regions, then performing a breakthrough operation to reach the lower portion, and finally conducting a second etching step to complete the trench. This segmentation allows precise control over which layers are removed at each stage, preventing electrical shorts while ensuring complete access to the active silicon region.
Solution Approach 2:
Before performing the final breakthrough etching operation, the process first etches dielectric layers and performs deposition cycles to prepare the structure. This preliminary action creates controlled access paths and protects surrounding areas, ensuring that when the breakthrough operation occurs, it precisely exposes the active silicon region without causing damage or electrical shorts.
2Reliability
If deposition cycles are performed to protect bitline structures, then polymer layers are formed, but additional etching steps are required to reach active silicon regions
Solution Approach 1:
A polymer layer is deposited as an intermediary protective material over the bitline structures during etching operations. This polymer layer acts as a mask that protects the bitline structures from being etched away while allowing the etching process to proceed on other areas. The polymer is later removed in a controlled breakthrough operation, enabling access to the active silicon region without permanently damaging the bitline structures.
3Manufacturing precision
If selective etching is performed to expose active silicon regions, then dielectric layers are differentially removed, but process control difficulty increases
Solution Approach 1:
The etching process utilizes parameter changes including pressure variations (from 5-40 mTorr in deposition to higher pressures in etching), temperature control, and RF power modulation to achieve selective removal of dielectric layers. By dynamically adjusting these parameters throughout the multi-step process, the system achieves precise control over which layers are etched at each stage, maintaining manufacturability despite the complexity of selective removal requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces electrical resistance and prevents shorts by ensuring accurate exposure of active silicon regions, improving the reliability and yield of memory device fabrication while maintaining the integrity of dielectric layers.
Implementation Method 1
deposition cycles of the deposition and etch cycles include supply of methane and argon. In other features, the deposition cycles include supplying the methane and argon at a pressure greater than or equal to 5 mT and less than or equal to 40 mT
Implementation Method 2
etch cycles of the deposition and etch cycles include supplying gases including (i) at least one of nitrogen fluoride, dichlorine, hexafluorobutadiene, fluoromethane, difluoromethane, or carbon tetrafluoride, and (ii) helium. In other features, etch cycles of the deposition and etch cycles include at least one of applying continuous wave or pulsing radio frequency signals to one or more electrodes
Implementation Method 3
While being etched, the substrate may be arranged on an electrostatic chuck (ESC) in a processing chamber of the corresponding substrate processing system
Data Source
AI summary
A substrate processing system includes a memory that stores a recipe of an electrical coupling process for electrical coupling a capacitor to an active silicon region of a memory structure. A system controller, according to the recipe, implements the at least a portion of the electrical coupling process including: performing deposition and etch cycles to remove a portion of one or more dielectric layers from a substrate, enlarge a trench between adjacent bitline structures of the memory structure, and provide access to a polymer layer or a dielectric layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation including etching at least one of the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etch operation to provide access for electrically coupling the capacitor to the active silicon region.