Semiconductor Memory Layer Offset for ON Current and Breakdown Resistance
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the configuration of conductive and semiconductor layers, leading to inefficiencies in electron channel formation and potential dielectric breakdown, particularly in the arrangement of drain side select transistors and inter-string unit insulating layers.
Innovation Solution
The semiconductor memory device employs a specific configuration where the central position of semiconductor layers does not coincide with the central position of adjacent layers, allowing for increased distance and thickness of conductive and insulating layers, ensuring proper voltage supply and reducing dielectric breakdown risks, along with a manufacturing method that adjusts the position of conductive layers and forms trench structures linearly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the central positions of semiconductor layers and adjacent conductive layers coincide, then the device structure is simpler and manufacturing is easier, but the distance between layers is insufficient leading to dielectric breakdown risks
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the central positions of semiconductor layers with adjacent conductive layers. This asymmetric configuration increases the distance between layers, reducing electric field concentration and preventing dielectric breakdown, while maintaining manufacturing feasibility through controlled offset positioning.
Solution Approach 2:
The patent transitions from a one-dimensional vertical stacking approach to a two-dimensional spatial arrangement by introducing lateral offsets between layers. This dimensional change allows increased inter-layer distance without increasing overall device height, effectively resolving the contradiction between reliability and structural simplicity.
2Reliability
If the distance between conductive layers is increased to prevent dielectric breakdown, then reliability improves, but the device area and manufacturing complexity increase
Solution Approach 1:
The patent utilizes lateral offset positioning in the horizontal plane to achieve increased vertical distance between conductive layers without expanding device footprint. This dimensional approach allows reliability improvement through greater spacing while maintaining compact device area.
Solution Approach 2:
The patent applies local quality by creating non-uniform spacing between layers through selective offset positioning. Different regions of the device have optimized inter-layer distances tailored to local electrical field requirements, achieving overall reliability improvement without uniform area expansion.
3Power
If the configuration of conductive and semiconductor layers is optimized for electron channel formation, then ON current improves, but the risk of dielectric breakdown increases due to reduced layer distances
Solution Approach 1:
The patent resolves this contradiction by implementing asymmetric offset positioning where semiconductor layer central positions are deliberately misaligned with adjacent conductive layers. This creates sufficient dielectric spacing to prevent breakdown while maintaining effective electron channel formation through controlled lateral positioning of the semiconductor channels.
Solution Approach 2:
The patent applies local quality by optimizing the offset distance to simultaneously satisfy two competing requirements: maintaining adequate spacing for dielectric breakdown prevention while preserving sufficient overlap for effective electron channel formation and high ON current. The local offset configuration balances electrical performance and reliability.
Data Source
AI summary
A semiconductor memory device comprises: first conductive layers arranged in a first direction; a first semiconductor layer facing the first conductive layers; a second semiconductor layer facing the first conductive layers; second conductive layers arranged in the first direction; third conductive layers arranged in the first direction; a third semiconductor layer facing the second conductive layers and connected to the first semiconductor layer; a fourth semiconductor layer facing the third conductive layers and connected to the second semiconductor layer; a fourth conductive layer facing the third semiconductor layer; and a fifth conductive layer connected to the third conductive layers. A distance from a central axis of the third semiconductor layer to a central axis of the fourth semiconductor layer is larger than a distance from a central axis of the first semiconductor layer to a central axis of the second semiconductor layer.