Semiconductor Memory Device Layer Parameter Segmentation

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in efficiently managing operation parameters for read and write operations across different conductive layers, leading to inconsistencies in cell characteristics and memory device performance.

Innovation Solution

The semiconductor memory device employs a configuration with multiple conductive layers and charge accumulating portions, where specific operation parameters are adjusted based on the conductive layer selected during read and write operations to ensure uniformity and improve memory device quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single operation parameter is used for all conductive layers, then the device complexity is reduced, but the manufacturing precision and cell characteristic uniformity deteriorate

Engineering Contradiction:
Improveoperation parameter managementVSAvoidcell characteristic uniformity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent divides the operation parameters into different sets corresponding to different conductive layers. Each conductive layer has its own optimized operation parameters (first operation parameters for first conductive layer, second operation parameters for second conductive layer), allowing precise control and uniform cell characteristics across layers while maintaining manageable complexity through systematic organization.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If different operation parameters are used for different conductive layers, then the cell characteristic uniformity is improved, but the device complexity increases

Engineering Contradiction:
Improvecell characteristic uniformityVSAvoidoperation parameter management
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements parameter changes by establishing distinct operation parameter sets for different conductive layers. The first operation parameters are specifically optimized for the first conductive layer, while the second operation parameters are optimized for the second conductive layer, enabling uniform cell characteristics across layers through targeted parameter optimization rather than arbitrary complexity increase.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for uniform read and write operations across different conductive layers, enhancing the consistency and quality of the semiconductor memory device by optimizing cell characteristics and operation efficiency.

Implementation Method 1

The gate insulating layer comprises a memory portion capable of storing data, such as an insulative charge accumulating film of the likes of silicon nitride (Si3N4) or a conductive charge accumulating film of the likes of a floating gate

Methodology Applied
Scientific EffectCharge accumulation: Electrical Accumulator

Data Source

PatentUS12243594B2Semiconductor memory device
Publication Date: 2025.03.04 KIOXIA CORP
  • US12243594B2 patent drawing
  • US12243594B2 patent drawing
  • US12243594B2 patent drawing

AI summary

A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.