3D Memory Device Source Line Segmentation for Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently programming and erasing transistors in multi-level coding due to limitations in threshold voltage distribution and operational complexity, particularly in three-dimensional stacked memory structures.
Innovation Solution
The semiconductor memory device incorporates a structure with multiple memory layers stacked on a substrate, featuring connection control transistors, drain select transistors, and source select transistors, where each memory layer shares bit lines but has electrically disconnected common source lines, enabling precise programming and erasing operations through controlled voltage applications and multi-level coding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple memory layers share common source lines, then device complexity is reduced, but threshold voltage distribution and operational reliability deteriorate
Solution Approach 1:
The patent divides the common source line into separate source lines for each memory layer. This segmentation allows independent voltage control for each layer, improving threshold voltage distribution and operational reliability while maintaining the benefits of a multi-layer structure.
2Manufacturing precision
If connection control transistors are added to each memory layer, then coding threshold voltage distribution improves, but device complexity increases
Solution Approach 1:
The patent applies connection control transistors selectively at specific locations within each memory layer where precise threshold voltage control is needed. This localized approach improves coding threshold voltage distribution while minimizing the overall increase in device complexity.
Solution Approach 2:
The connection control transistors serve multiple functions: they control the connection between memory cells and bit lines, enable multi-level coding operations, and facilitate precise threshold voltage distribution. This multi-functionality justifies the added complexity by delivering multiple benefits from a single component.
3Productivity
If multi-level coding is implemented, then memory capacity and efficiency increase, but operational complexity increases
Solution Approach 1:
The patent performs preliminary programming of connection control transistors before main memory operations. This preliminary action prepares the memory structure for efficient multi-level coding by establishing proper initial threshold voltage distributions, thereby reducing the complexity of subsequent programming and erasing operations.
Data Source
AI summary
A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory layers stacked on a semiconductor substrate, wherein each of the plurality of memory layers includes one or more connection control transistors, one or more drain select transistors, a plurality of memory cells, and a source select transistor electrically coupled in series between a plurality of bit lines and a common source line, and the plurality of memory layers share the plurality of bit lines, and the common source lines electrically coupled to each of the plurality of memory layers are electrically disconnected.