Semiconductor Memory Layout With 3D Wiring for Faster Access
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in optimizing the layout and connectivity of memory cells and peripheral circuits, leading to inefficiencies in data storage and retrieval processes.
Innovation Solution
The semiconductor memory device incorporates a substrate with distinct first and second regions, featuring a first wiring extending in one direction and a second wiring intersecting, along with memory cells connected to these wirings and contact electrodes, optimizing the layout to enhance data storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells and peripheral circuits are integrated on a single substrate with conventional layout, then device complexity is reduced, but data access speed and power consumption are compromised
Solution Approach 1:
The substrate is divided into a first region for memory cells and a second region for peripheral circuits, with distinct wiring arrangements in each region. This segmentation allows optimized signal paths for high-speed access while isolating peripheral circuit operations, resolving the contradiction between speed and complexity.
Solution Approach 2:
The patent introduces a three-dimensional wiring structure with wirings extending in multiple directions (first direction, second direction, third direction) and across multiple layers. This dimensional expansion enables efficient connectivity between memory cells and peripheral circuits without increasing planar layout complexity.
2Productivity
If wiring density is increased to improve connectivity, then data retrieval efficiency improves, but power consumption increases
Solution Approach 1:
Different wiring configurations are applied to different regions: the first region uses wirings optimized for high-density memory access, while the second region uses wirings optimized for peripheral circuit connectivity. This local optimization achieves high retrieval efficiency without uniformly increasing power consumption across the entire device.
Solution Approach 2:
The patent employs multiple wiring layers and contact electrodes to create equipotential connections, reducing voltage drops and resistive losses in high-density wiring regions. This maintains efficient data retrieval while minimizing the power penalty associated with increased wiring density.
3Area of stationary object
If memory cells are densely packed to increase storage capacity, then area utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes multi-layer wiring structures where connections are established through vertical contacts between layers rather than solely through planar routing. This three-dimensional approach enables dense memory cell packing while maintaining manufacturable wiring alignment tolerances through stacked interconnects rather than highly complex planar patterns.
Data Source
AI summary
A semiconductor memory device includes a substrate including a first region and a second region arranged in a first direction, a first wiring extending in the first direction across the first region and the second region, a second wiring disposed in the first region and extending in a second direction that intersects with the first region, a first semiconductor layer disposed in the first region, electrically connected to the second wiring, and opposed to the first wiring, a memory unit electrically connected to the first semiconductor layer, and a contact electrode extending in a third direction intersecting with a surface of the substrate, and connected to the first wiring. The contact electrode includes a first part that overlaps with the first wiring viewing from the third direction, and a second part that does not overlap with the first wiring viewing from the third direction.