Memory Cell Layout Using Cross-Extended Gates for Higher Density
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Solution Overview
Problem
As semiconductor components continue to miniaturize, reaching physical limits in integration density due to shrinking geometries, there is a need for innovative solutions to enhance memory device performance and reduce footprint while maintaining operational efficiency.
Innovation Solution
The design incorporates a memory device with gate-all-around transistors and single-dimensional bridging components, such as butted contacts, which reduce footprint area and improve electrical connections, allowing for more efficient routing and reduced resistance, enabling faster operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional miniaturization approaches are continued, then integration density improves, but physical limits are reached due to geometries shrinking to less than ten atomic layers
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to 3D vertically-stacked transistor architectures. Multiple transistor layers are stacked above each other, utilizing the vertical dimension to increase integration density without further reducing lateral feature sizes. This dimensional transition allows continued scaling beyond conventional planar limits.
Solution Approach 2:
The patent implements nested structures where smaller components are positioned within or around larger ones. Specifically, gate structures wrap around channel regions in gate-all-around configurations, and multiple transistor layers are stacked within a shared footprint area, creating a nested arrangement that maximizes space utilization.
2Quantity of substance
If feature sizes are reduced to increase integration density, then more components fit in the same area, but manufacturing precision becomes increasingly difficult to maintain
Solution Approach 1:
The patent divides the transistor structure into multiple discrete layers (channel layers, gate layers, source/drain layers) that can be formed and patterned separately at larger dimensions, then assembled vertically. This segmentation allows each layer to be manufactured with relaxed precision requirements, avoiding the need to pattern entire transistor arrays at ultra-fine dimensions in a single step.
Solution Approach 2:
By moving critical functions to the vertical dimension (stacked layers), the patent reduces the lateral footprint requirements. This allows lateral feature sizes to be maintained at manufacturable dimensions while achieving high integration density through vertical stacking, thereby decoupling integration density from lateral manufacturing precision requirements.
3Reliability
If deeper vias are used for routing connections in miniaturized devices, then electrical connections can be maintained, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent routes electrical connections primarily through the vertical dimension using stacked contact structures and via holes between layers, rather than relying on long lateral via paths. This vertical routing approach shortens connection lengths and reduces the number of deep via layers required, simplifying the overall interconnection architecture while maintaining electrical reliability.
Data Source
AI summary
A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.