Memory Device Layout with Dummy Gates and Recessed Landing Pads
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Solution Overview
Problem
Conventional flash memory devices face reliability issues due to misalignment between select gates and contact plugs, particularly with the shrinkage of device size and process window, leading to failed memory devices when using a spacer-typed select gate approach.
Innovation Solution
The layout and semiconductor structure incorporate dummy gates and select gate landing pads with a recessed flat surface, allowing for infallible contact between select gate contact plugs and the landing pads, improving alignment accuracy and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is shrunk to improve integration density, then productivity increases, but manufacturing precision deteriorates due to misalignment between select gate and contact plugs
Solution Approach 1:
The patent introduces dummy gates and recessed landing pads as preliminary structural features that are formed before final alignment operations. The recessed landing pads create a geometric feature that guides contact plug formation, ensuring proper alignment is achieved before the actual contact is made, thus preventing misalignment issues during device shrinkage
Solution Approach 2:
The dummy gates serve as intermediary structures that facilitate the alignment process. By creating a reference structure (dummy gate) with a specific geometric relationship to the landing pad, the system provides an intermediate alignment target that is easier to align with than the actual contact plug, thereby improving overall alignment precision
2Device complexity
If spacer-typed select gate approach is used to simplify structure, then device complexity is reduced, but reliability deteriorates due to sloped profile preventing infallible contact
Solution Approach 1:
The patent applies local quality by creating a recessed region with a flat bottom surface specifically at the contact area of the landing pad. While the overall landing pad structure remains simple, the local geometry at the contact point is modified to provide a flat surface that ensures infallible contact with the contact plug, thereby improving reliability without significantly increasing overall device complexity
Solution Approach 2:
Instead of making the select gate structure more complex to achieve flat contact, the patent inverts the approach by creating a recess in the landing pad structure. This inversion allows the contact plug to reliably contact the flat bottom surface of the recess, solving the contact reliability issue while maintaining the simplicity of the spacer-typed select gate approach
Data Source
AI summary
A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.