Memory Data Layout Using Latency-Aware Address Mapping

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory systems often hide the physical organization of memory allocation from the host system, leading to inefficient memory access due to unknown latency costs across different memory boundaries.

Innovation Solution

A memory manager provides performance records indicating latency for subsets of addresses within the memory space, allowing the host system to sort and store data based on these records, optimizing data layout for efficient memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If memory systems hide the physical organization of memory allocation from the host system, then memory management complexity is reduced, but memory access efficiency deteriorates due to unknown latency costs

Engineering Contradiction:
Improvememory management complexityVSAvoidmemory access efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces performance records as an intermediary mechanism that bridges the host system and memory manager. These records convey latency information about memory boundaries without requiring the memory manager to expose complex physical organization details, thus maintaining simplicity while enabling efficient data layout optimization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The memory manager provides feedback to the host system through performance records that indicate latency costs for accessing different memory boundaries. This feedback loop enables the host system to adjust data layout strategies based on actual memory access characteristics, improving efficiency without increasing management complexity.

Inventive Principle:
Principle #23Feedback

2Ease of manufacture

If the host system does not know latency costs across memory boundaries, then memory allocation is simplified, but data layout optimization is limited

Engineering Contradiction:
Improvememory allocation simplicityVSAvoiddata layout optimization
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The memory manager performs preliminary action by pre-calculating and recording performance information about memory boundaries before the host system needs to optimize data layout. These pre-computed performance records are made available to the host system, enabling optimization without requiring complex real-time analysis.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Performance records serve as an intermediary that translates complex memory boundary latency information into a format the host system can easily process and use for optimization decisions, maintaining allocation simplicity while enabling sophisticated data layout strategies.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If data is stored without considering memory boundary latency, then storage operations are faster, but memory access latency increases due to suboptimal data layout

Engineering Contradiction:
Improvestorage operation speedVSAvoidmemory access latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The host system performs preliminary sorting and reorganization of data based on performance records before actual memory access operations occur. This preliminary action optimizes data layout in advance, ensuring that frequently accessed data is positioned to minimize future access latency without slowing down storage operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts data layout strategies based on the specific memory access patterns and performance characteristics of different memory boundaries. This dynamic optimization allows the system to adapt data organization to actual usage patterns, reducing access latency without compromising storage speed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250383988A1Systems for software optimization of data layout
Publication Date: 2025.12.18 MICRON TECHNOLOGY INC
  • US20250383988A1 patent drawing
  • US20250383988A1 patent drawing
  • US20250383988A1 patent drawing

AI summary

Methods, systems, and devices for systems for software optimization of data layout are described. A memory manager may indicate an allocation of a memory space and performance records that indicate latency information for ranges of addresses within a memory space of a memory system. For example, the memory manager may allocate a physical region of memory that includes memory boundaries. Accessing memory within the different memory boundaries may correspond to varying latency costs. Thus, the performance records may indicate to the host system a mapping between the ranges of addresses within the memory space and the corresponding latency cost associated with accessing an address within the range. In some examples, a host system may sort data for storage within the memory system based on the performance records associated with the allocated memory space.