Semiconductor Memory Layout With Perpendicular Bitline-Wordline Routing
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Solution Overview
Problem
As memory technology advances, it becomes increasingly difficult to increase storage capacity while reducing memory size, leading to challenges in reducing mutual interference between components and maintaining stability.
Innovation Solution
A semiconductor structure is designed with a wordline and bitlines arranged such that the extension direction of the first bitline is perpendicular to the wordline, reducing mutual interference and allowing for increased storage capacity by efficiently utilizing internal space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory size is reduced to increase storage capacity, then storage capacity increases, but mutual interference between components increases and stability deteriorates
Solution Approach 1:
The patent transitions from a conventional planar arrangement where bitlines are parallel to wordlines to a three-dimensional configuration where bitlines are positioned perpendicular to wordlines. This dimensional change allows memory components to be stacked vertically, increasing storage capacity without reducing the footprint area, thereby maintaining component spacing and stability while achieving higher density.
Solution Approach 2:
The patent implements a nested structure where memory structures are stacked vertically above the transistor and bitline, creating a multi-layer configuration. This nesting approach allows multiple memory cells to occupy the same horizontal footprint by utilizing vertical space, effectively increasing storage capacity without compromising the spatial separation needed to reduce mutual interference.
2Quantity of substance
If memory size is reduced to increase storage capacity, then storage capacity increases, but mutual interference between wordline and bitline increases
Solution Approach 1:
By repositioning the bitline from a horizontal arrangement (parallel to wordline) to a vertical arrangement (perpendicular to wordline), the patent eliminates the overlapping area between wordline and bitline. This dimensional reconfiguration reduces capacitive coupling and electromagnetic interference while maintaining electrical connectivity, thus reducing mutual interference without sacrificing storage capacity.
Solution Approach 2:
The patent extracts the bitline from the conventional planar intersection with the wordline and repositions it to a perpendicular configuration. This separation removes the source of mutual interference (the overlapping region) while preserving the functional connection between the bitline and memory structures through vertical alignment and contact structures.
Data Source
AI summary
Embodiments of the present application provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a wordline; and a first bitline and a second bitline located on two sides of the wordline and a first memory structure and a second memory structure located on the two sides of the wordline. The first bitline and the second bitline are connected to the first memory structure and the second memory structure respectively through a transistor. An extension direction of the first bitline is perpendicular to an extension direction of the wordline.