Memory Data Layout Reordering for QLC Read Efficiency
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Solution Overview
Problem
Memory systems face challenges with increased write buffer size and complexity due to big-z data layout schemes, particularly when using quad-level cells (QLC), which can be unsustainable for some systems.
Innovation Solution
Implementing a two-stage data layout scheme where data is initially written using a little-z layout to a first set of memory cells (SLCs, MLCs, or TLCs) with a smaller buffer, and then transferred and reordered during idle time to a second set of QLCs for a big-z layout, reducing write buffer size while maintaining efficient read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a big-z data layout scheme is used for write operations to QLCs, then read operation efficiency is improved, but write buffer size and system complexity increase
Solution Approach 1:
The patent segments the write operation into two distinct phases: a first write operation using little-z layout to intermediate memory locations, and a second write operation using big-z layout to final QLC locations. This segmentation allows the system to achieve big-z read efficiency without requiring a large write buffer, as data is first written to intermediate locations with smaller buffer requirements, then transferred to final locations during idle periods.
Solution Approach 2:
The patent performs preliminary writing to intermediate memory locations using little-z layout before the final write to QLCs. During idle periods, data is transferred and reordered from intermediate locations to final locations. This preliminary action allows the system to prepare data for efficient reads without requiring large buffers during the actual write operation.
2Productivity
If data is written directly to QLCs using big-z layout, then read operations are optimized, but write operations become slower with larger buffer requirements
Solution Approach 1:
The write operation is divided into two segments: first writing to intermediate memory locations with little-z layout (faster, smaller buffer), then transferring to final QLC locations with big-z layout (slower, larger buffer). This segmentation enables the system to prioritize write speed by using the faster little-z path initially, while still achieving optimized read performance through the subsequent big-z reordering.
Solution Approach 2:
The patent introduces intermediate memory locations as a mediator between the host system and final QLC storage. Data flows through this intermediary layer first, allowing fast writes with minimal buffering, then is gradually transferred to final locations during idle periods. This intermediary approach decouples the write speed requirement from the read optimization requirement.
3Device complexity
If a two-stage data layout scheme is implemented, then write buffer size is reduced, but additional data transfer operations are required
Solution Approach 1:
The patent implements periodic transfer operations during idle periods between host write commands. Instead of continuously transferring data, the system utilizes naturally occurring idle time windows to perform the reordering and transfer from intermediate to final locations. This periodic action minimizes the impact on overall system performance while still achieving the buffer size reduction benefit.
Solution Approach 2:
The system performs data reordering and transfer operations during its own idle periods without requiring additional dedicated transfer hardware or external intervention. The memory controller autonomously manages the two-stage write process, utilizing its own idle time to perform the data movement, thereby converting what would be wasted time into productive reordering operations.
Data Source
AI summary
Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.