Symmetric Memory Cell Layout to Prevent Erase-Source Shorting

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Solution Overview

Problem

Existing split-gate flash memory cells require a source line contact on the strap cell between two adjacent control gate lines, leading to potential shorting between the erase gate line and the source line.

Innovation Solution

A semiconductor memory device with a substrate and device lines comprising a select gate, control gate, erase gate, and source line, featuring an asymmetric active area layout with a strap cell and aligned bit line and source line contacts, and varying gate dielectric layers to prevent shorting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a source line contact is provided on the strap cell between two adjacent control gate lines, then the strap cell can be electrically connected, but shorting between the erase gate line and the source line may occur

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidshorting between erase gate line and source line

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent removes the source line contact from the strap cell area and relocates it to the source line contact region. This extraction eliminates the harmful shorting path between the erase gate line and source line while preserving the necessary electrical connection function through the relocated contact.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a discontinuity in the erase gate line as an intermediary barrier between the source line contact and the erase gate line. This discontinuity acts as a mediator that prevents direct electrical connection (shorting) between the source line and erase gate line while allowing the strap cell to function properly.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the second gate dielectric layer is made thicker than the first gate dielectric layer, then the strap cell can be protected from shorting, but the manufacturing precision requirements increase

Engineering Contradiction:

Improveshorting preventionVSAvoidgate dielectric layer thickness control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies different gate dielectric layer thicknesses to different regions: a thicker second gate dielectric layer in the strap cell region for enhanced protection against shorting, and a thinner first gate dielectric layer in the memory cell region for standard operation. This local differentiation optimizes both reliability and manufacturing feasibility.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12477727B2Semiconductor memory device having a symmetric active area layout structure

Publication Date: 2025.11.18 UNITED MICROELECTRONICS CORP

AI summary

A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.