3D Memory Cell Layout With Staggered Contacts for Voltage Transfer
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in efficiently transferring voltage across memory blocks due to long distances and complex wiring patterns, which can lead to dielectric breakdown and increased circuit area.
Innovation Solution
The semiconductor memory device incorporates a staggered pattern of contact and through contact regions, reducing the distance between transistors and contacts, and optimizing the arrangement of conducting layers and transistors to minimize voltage differences across insulating layers, thereby reducing dielectric breakdown risk without increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wiring patterns are used to transfer voltage across memory blocks, then voltage transfer can be achieved, but the distance is long and wiring patterns are complex, leading to dielectric breakdown and increased circuit area
Solution Approach 1:
The patent segments the transistor arrays into multiple blocks (first transistor array and second transistor array) with corresponding contact regions and through contact regions arranged in a staggered pattern. This segmentation allows voltage to be transferred through shorter, distributed paths rather than long centralized wiring, reducing both complexity and dielectric breakdown risk
Solution Approach 2:
The patent utilizes a three-dimensional stacked architecture where memory cell arrays are disposed separately from the semiconductor substrate in a direction intersecting with the substrate surface. This vertical dimensionality change enables shorter horizontal wiring distances and more efficient voltage transfer paths across memory blocks
2Reliability
If conventional wiring patterns are used to transfer voltage across memory blocks, then voltage transfer can be achieved, but the distance is long, leading to increased circuit area
Solution Approach 1:
By dividing the transistor arrays into multiple blocks with staggered contact regions, the patent creates shorter voltage transfer paths within each block. This segmentation reduces the total distance voltage must travel compared to conventional long-distance wiring patterns, thereby improving transfer efficiency without requiring additional circuit area
Solution Approach 2:
The patent merges the functions of contact regions and through contact regions into a unified staggered arrangement that serves both voltage input and through-conduction purposes. This integration eliminates the need for separate long-distance wiring paths, reducing circuit area while maintaining efficient voltage transfer
3Productivity
If transistors are arranged close to contacts, then voltage transfer distance is reduced, but voltage differences across insulating layers increase, risking dielectric breakdown
Solution Approach 1:
The patent applies local quality by creating alternating regions with different functions: contact regions where transistors receive voltage inputs, and through contact regions where voltage is conducted to adjacent blocks. This local differentiation allows transistors to be positioned close to contacts for fast transfer while the staggered arrangement ensures voltage differences across insulating layers are distributed and reduced, preventing dielectric breakdown
Data Source
AI summary
A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.