Memory Sub-System LBA Reconfiguration for Sub-Block Data Access
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Solution Overview
Problem
Conventional memory sub-systems face inefficiencies in data transfer and memory usage due to read and memory amplification caused by accessing data at block levels that exceed the spatial locality of the data needed, particularly in applications like graph structures and massive deep learning recommendation models, where the data size is smaller than the typical logical block size.
Innovation Solution
Implementing sub block access techniques that allow data transfer and storage at a granularity level lower than the block level by adjusting the Logical Block Addressing (LBA) size to match the size of sub blocks, using error correction code (ECC) protection at the block level and enabling efficient access and transfer of only the necessary data portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is accessed at block level in conventional memory sub-systems, then error correction code protection can be applied, but read amplification and memory amplification occur because the data size exceeds the spatial locality of the needed data
Solution Approach 1:
The patent divides a logical block into multiple sub-blocks, each accessible independently. This segmentation allows the system to retrieve only the specific sub-block containing the needed data rather than reading the entire block, thereby reducing read amplification and memory amplification while maintaining ECC protection at the block level
Solution Approach 2:
The patent extracts and transfers only the useful data portion (specific sub-block) from the larger logical block to the host system. This extraction eliminates the transfer of unnecessary data that would otherwise occur with block-level access, reducing both read amplification and memory amplification
2Productivity
If logical block addressing size is reduced to match sub block size, then only necessary data portions can be transferred, but the complexity of address mapping and data management increases
Solution Approach 1:
The patent introduces a translation layer that maps sub-block-level logical addresses to block-level physical addresses. This intermediary mapping mechanism enables fine-grained data access while abstracting the complexity from the host system, as the memory sub-system handles the address translation internally
3Power
If block level access is used, then error correction code operations are efficient, but data transfer includes unnecessary data outside the useful portion
Solution Approach 1:
By segmenting the logical block into multiple sub-blocks with independent access, the system can retrieve only the specific sub-block containing useful data. This segmentation enables precise data extraction while maintaining block-level ECC operations, preventing the transfer of useless data outside the useful portion
Data Source
AI summary
A computing system having a host system connected to a memory sub-system via a computer bus. In response to the host system sending a first command configured to identify a first logical block addressing data size at a block level, the memory sub-system can format data storage for a namespace in a non-volatile memory at the block level. In response to the host system sending a second command configured to identify a second logical block addressing data size at a sub block level, the memory sub-system can configure access to the namespace at the second logical block addressing data size without changing the data storage in the non-volatile memory for the namespace at the block level.