Computational Memory LDPC Decoder for High-Throughput Error Correction
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Solution Overview
Problem
Existing LDPC decoders face inefficiencies in error correction due to reliance on external processing and decoding circuitry, which limits throughput and increases chip size and power consumption.
Innovation Solution
Implementing an LDPC decoder using a computational memory array with variable and check node sections, where each cell can perform operations and store data, and a controller to manage data transfer and processing, allowing parallel data transfer and reduced external dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external processing and decoding circuitry are used in existing LDPC decoders, then error correction can be performed, but throughput is limited and chip size and power consumption increase
Solution Approach 1:
The patent merges the processing and memory functions into a single computational memory array where memory cells perform both storage and decoding operations. This integration eliminates the need for separate external processing circuitry, thereby increasing throughput while reducing chip size and power consumption.
Solution Approach 2:
The computational memory cells are designed to be multi-functional, serving as both storage elements and processing units. Each memory cell can store data bits and simultaneously perform decoding operations, allowing the same hardware structure to handle multiple functions without requiring additional dedicated circuitry.
2Reliability
If external processing and decoding circuitry are used in existing LDPC decoders, then error correction can be performed, but power consumption increases
Solution Approach 1:
By combining memory and processing functions into a single computational memory array, the patent eliminates the need for data transfer between separate memory and processing units. This reduces the overall power consumption while maintaining error correction capability, as the same cells perform both storage and decoding operations in place.
3Productivity
If computational memory array with integrated processing is used, then throughput increases and chip size reduces, but device complexity increases
Solution Approach 1:
The computational memory array is segmented into variable node sections and check node sections, each handling specific decoding operations. This segmentation allows the complex decoding process to be divided into manageable parts that can be executed in parallel, reducing the complexity of individual cells while maintaining high throughput.
Solution Approach 2:
The memory cells are designed to autonomously perform decoding operations without requiring complex external control circuitry. Each computational memory cell contains the logic to perform its own processing functions, simplifying the overall device architecture while enabling high-speed parallel operation.
Data Source
AI summary
An error correction code decoder, including a computational memory array having at least a variable node section, a check node section, and a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on the bit and each cell implementing one node. A controller instructs the computational memory to perform the operations and to write the results of computations on a block of variable nodes into associated set of blocks of check nodes and to write the results of computations on a block of check nodes into associated set of blocks of variable nodes.