Memory Programming Level Compaction for Erase Disturb Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The all levels programming process in memory devices results in undesirable extension or widening of erase and first programming level distributions, leading to reduced reliability and performance due to high pass voltage levels causing erase disturb and band-to-band tunneling leakage.

Innovation Solution

Implement a two-phase programming approach where a first subset of programming levels (L2 to LM) is programmed in a first sub-phase, followed by programming the second subset (L1) during a subsequent sub-phase, with inhibited programming of L1 during the initial pulses, optimizing the read budget window and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all levels programming is performed simultaneously using high pass voltage, then programming speed is improved, but erase disturb and band-to-band tunneling leakage increase causing distribution widening

Engineering Contradiction:

Improveprogramming speedVSAvoiddistribution compactness

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The programming operation is divided into two distinct phases: a first phase that programs levels L2 to LM, and a second phase that programs level L1. This segmentation allows different voltage conditions to be applied to different level subsets, preventing the distribution widening that occurs when all levels are programmed simultaneously with high pass voltage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Levels L2 to LM are programmed in advance during the first phase before programming level L1 in the second phase. This preliminary action allows the higher levels to be established under optimized voltage conditions, preventing the erase disturb and band-to-band tunneling leakage that would occur if all levels were programmed simultaneously with high pass voltage.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If high pass voltage is applied during all levels programming, then programming efficiency is improved, but erase disturb occurs reducing memory reliability

Engineering Contradiction:

Improveprogramming efficiencyVSAvoiderase disturb

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The programming operation is divided into two distinct phases: a first phase that programs levels L2 to LM, and a second phase that programs level L1. This segmentation allows different voltage conditions to be applied to different level subsets, preventing the erase disturb that occurs when all levels are programmed simultaneously with high pass voltage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent converts the potentially harmful high pass voltage effect into a beneficial outcome by applying it selectively only to levels L2-LM in the first phase, while using different voltage conditions for level L1 in the second phase. This selective application eliminates erase disturb while maintaining programming efficiency for the affected levels.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Loss of time

If simultaneous all levels programming is performed, then time consumption is reduced, but distribution widening occurs reducing read window budget

Engineering Contradiction:

Improveprogramming timeVSAvoidprogramming distribution compactness

Core Design Contradiction:

Loss of timeVSManufacturing precision

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20260011373A1Selected programming level compaction during all levels programming of a memory device

Publication Date: 2026.01.08 MICRON TECHNOLOGY INC

AI summary

Control logic in a memory device initiates a program operation including application of a set of programming pulses to a wordline associated with one or more memory cells of a memory array to be programmed to a set of programming levels. During a first sub-phase of the programming operation, the control logic causes each programming pulse to program a first subset of programming levels, wherein programming of a second subset of one or more programming levels is inhibited. During a second sub-phase of the programming operation, the control logic programs the second subset of one or more programming levels, where the second subset of one or more of the plurality of programming levels are associated with one or more lower voltage levels than the first subset of the plurality of programming levels.