Cascaded Memory Level Shifter Using Low-Voltage MOSFETs
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Solution Overview
Problem
The use of level shifters in semiconductor memory devices requires both low- and high-voltage transistors, leading to increased chip area and manufacturing complexity due to the need for thicker gate oxide layers in high-voltage transistors and additional processing steps for differentiating oxide thickness.
Innovation Solution
A level shifter design utilizing low-voltage transistors with cascaded stages, where input and output transistors are p-channel MOSFETs and interface transistors are n-channel MOSFETs, allowing for voltage shifting without the need for high-voltage transistors, thereby reducing chip area and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage transistors with thicker gate oxide layers are used in level shifters, then the device can sustain higher voltage differences, but the chip area increases and manufacturing complexity increases
Solution Approach 1:
The level shifter is divided into multiple stages, each handling a portion of the voltage conversion. This segmentation allows each transistor to operate within safe voltage limits while achieving overall high-voltage capability through the cascaded structure.
Solution Approach 2:
Intermediate voltage nodes are introduced between the input and final output, allowing gradual voltage transformation. These intermediary points enable the use of low-voltage transistors by breaking down the large voltage difference into smaller, manageable steps.
2Reliability
If high-voltage transistors with thicker gate oxide layers are used in level shifters, then the device can sustain higher voltage differences, but the manufacturing process complexity increases due to additional processing steps
Solution Approach 1:
The level shifter design uses a universal transistor structure that can handle both low and intermediate voltages. This multi-functionality eliminates the need for separate high-voltage transistor fabrication processes, as the same transistor design serves multiple voltage levels throughout the cascaded stages.
Solution Approach 2:
The invention changes the operating parameters (voltage levels) rather than the physical structure of the transistors. By adjusting voltage parameters across different stages and using appropriate transistor sizing, the system achieves high-voltage capability without requiring physical modifications to the transistor oxide layers.
3Area of stationary object
If low-voltage transistors are used in level shifters, then the chip area is reduced and manufacturing is simplified, but the device cannot sustain high voltage differences
Solution Approach 1:
The voltage conversion is segmented into multiple smaller steps, each handled by low-voltage transistors operating within their safe voltage limits. The cascaded architecture ensures that no single transistor experiences excessive voltage stress while collectively achieving the required voltage transformation.
Solution Approach 2:
The solution transitions from a single-stage voltage conversion to a multi-dimensional cascaded structure. By adding the temporal dimension of staged operation and spatial dimension of multiple intermediate nodes, the system achieves high-voltage capability through a series of low-voltage steps rather than a single high-voltage jump.
Data Source
AI summary
A level shifter is proposed. The level shifter includes a stage having a first branch and a second branch, each branch including: a selection terminal for receiving a selection signal, the selection signal received by the first branch and the second branch being alternatively at a first voltage and at a second voltage higher than the first voltage in absolute value, a service terminal for receiving a third voltage higher than the second voltage in absolute value, an input circuit for coupling an intermediate node to the selection terminal when at the second voltage or for insulating the intermediate node from the selection terminal otherwise, an interface circuit for coupling an output terminal to the intermediate node when coupled or for insulating the output terminal from the intermediate node otherwise, and an output circuit for insulating the service terminal from the output terminal when coupled or for coupling the service terminal to the output terminal otherwise, the output terminals of the first branch and the second branch providing an output signal being alternatively at the second voltage or at the third voltage according to the selection signal.