Memory Level Shifter Circuit for Faster Voltage Translation
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Solution Overview
Problem
Memory systems face challenges in efficiently shifting voltage levels between memory devices and controllers, leading to performance and reliability issues due to differing power supply voltages, which existing level shifters fail to address effectively.
Innovation Solution
A level shifter is designed with a pull-up unit, pull-down unit, and discharge/charge units to rapidly switch and adjust output signal levels, incorporating PMOS and NMOS transistors to supply internal power or ground voltage and manage potential levels, thereby facilitating efficient signal transmission between memory devices and controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifters are used to change voltage levels between memory devices and controllers, then voltage level shifting is achieved, but switching speed is insufficient and circuit area is large
Solution Approach 1:
The level shifter is divided into separate pull-up units and pull-down units, each independently controlling different output nodes. This segmentation allows parallel operation of multiple transistors, reducing overall switching time while maintaining signal integrity for reliable transmission.
Solution Approach 2:
The pull-up units are configured to activate before the pull-down units complete their discharge action. This preliminary action ensures that the output voltage reaches the target level quickly, improving switching speed while the coordinated operation maintains signal reliability.
2Reliability
If conventional level shifters are used to change voltage levels, then voltage level shifting is achieved, but the circuit area occupied is large
Solution Approach 1:
Multiple PMOS transistors are merged into a single pull-up unit structure, and multiple NMOS transistors are merged into a single pull-down unit structure. This consolidation reduces the total circuit area while maintaining the reliable signal transmission function through coordinated transistor operation.
Solution Approach 2:
The pull-up units and pull-down units serve multiple functions: voltage level shifting, signal buffering, and timing control. This multi-functionality reduces the need for additional dedicated circuits, thereby reducing overall circuit area while ensuring reliable signal transmission.
3Area of stationary object
If transistor size is reduced to decrease circuit area, then circuit area is reduced, but switching speed decreases
Solution Approach 1:
The circuit is segmented into parallel pull-up and pull-down units that operate simultaneously. This segmentation allows the use of smaller transistors with faster switching characteristics, as the parallel architecture compensates for individual transistor size reduction, maintaining overall switching speed while reducing circuit area.
Solution Approach 2:
The circuit employs dynamic control of transistor switching through the coordinated operation of pull-up and pull-down units. This dynamic operation allows smaller transistors to achieve effective switching by utilizing the temporal coordination of multiple units, thereby reducing circuit area without sacrificing switching speed.
Data Source
AI summary
There are provided a level shifter and a memory system including the same. The level shifter includes: a pull-up unit for supplying an internal power supply voltage to a first output node or a second output node in response to an input signal and an inverted input signal; a pull-down unit for applying a ground voltage to the first output node or the second output node in response to potential levels of the first output node and the second output node; and a discharge unit for discharging the potential level of the first output node or the second output node in response to the input signal and the inverted input signal.