3D Memory Conductive Levels With β-Phase Tungsten for Tier Scaling
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density due to decreased conductivity of conductive structures as the thickness of tiers decreases, affecting the performance of memory cells in terms of threshold voltage and erase voltage.
Innovation Solution
The implementation of a microelectronic device structure with a stack of vertically alternating insulative and conductive levels, where the conductive levels include a first conductive structure and a second conductive structure with a larger grain size of β-phase tungsten, enhancing conductivity and facilitating improved performance of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of each tier is decreased to increase the number of tiers within a given height of the stack, then memory density is improved, but the resistivity of the conductive structures increases and conductivity decreases
Solution Approach 1:
The patent applies local quality by creating two distinct conductive structures within the same conductive level: a first conductive structure with a work function optimized for memory cell performance, and a second conductive structure with enhanced conductivity to compensate for the reduced tier thickness. This local differentiation allows each structure to fulfill specific functional requirements that would be impossible to achieve with a uniform material composition throughout the entire conductive level.
2Quantity of substance
If the thickness of each tier is decreased to increase the number of tiers within a given height of the stack, then memory density is improved, but the threshold voltage and erase voltage performance deteriorates
Solution Approach 1:
The first conductive structure is specifically engineered with a work function tailored for optimal memory cell operation, including appropriate threshold voltage and erase voltage characteristics. This localized optimization ensures that despite the reduced tier thickness, the memory cell performance parameters remain within acceptable ranges.
Solution Approach 2:
The conductive level is formed as a composite structure combining two different conductive materials or material compositions. The first conductive structure uses a material optimized for electrical work function properties, while the second conductive structure uses a material optimized for high conductivity. This composite approach allows the system to achieve both high memory density and proper voltage characteristics simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the conductivity of the conductive levels, thereby improving the performance of memory cells by maintaining or enhancing the conductivity relative to conventional structures, even as the thickness of tiers decreases, thus addressing the issue of decreased conductivity in conventional vertical memory arrays.
Implementation Method 1
the second conductive structures may exhibit a larger grain size than the grain size of the first conductive structures, facilitating an increased conductivity of the second conductive structures relative to the first conductive structures
Data Source
AI summary
A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.