Bidirectional Memory Line Buffers for Faster Multi-Bank Arrays

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Solution Overview

Problem

As memory devices increase in capacity by adding more banks, the length of signal lines such as LDRW lines, digit lines, and word lines also increases, leading to higher capacitance and resistance, which slows down operating speed, creating a need for faster signal coupling methods without compromising capacity.

Innovation Solution

Implementing bidirectional buffers between segments of signal lines, such as LDRW lines, digit lines, and word lines, to facilitate efficient signal transfer in both directions without the need for decoding circuitry, reducing circuitry requirements and enhancing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of memory banks is increased to increase capacity, then the memory capacity is improved, but the length of signal lines increases leading to higher capacitance and resistance which reduces operating speed

Engineering Contradiction:
Improvememory capacityVSAvoidoperating speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The signal line is divided into multiple segments with buffers inserted between them. Each buffer segment handles a portion of the total signal line length, reducing the capacitance and resistance that any single segment must drive. This segmentation allows the system to maintain high operating speeds while supporting increased memory capacity through additional banks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Buffers are inserted as intermediary components between segments of the signal line. These buffers act as mediators that regenerate and re-drive the signal, reducing the cumulative effect of capacitance and resistance over long signal line lengths. This allows signal integrity to be maintained across extended distances needed for higher capacity configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If bidirectional buffers are used for signal coupling, then the operating speed is improved, but the circuitry complexity increases

Engineering Contradiction:
Improvesignal coupling speedVSAvoidcircuitry complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The buffer circuit is designed to operate bidirectionally, serving as a universal component that can drive signals in either direction along the signal line. This multi-functionality eliminates the need for separate unidirectional buffers for each direction, reducing overall circuitry complexity while maintaining high signal coupling speeds.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The buffer combines multiple functions into a single circuit element: signal amplification, direction control, and impedance matching. By merging these functions, the design achieves high-speed bidirectional signal coupling without requiring multiple separate components, thus reducing overall circuitry complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20100177571A1Memory bank signal coupling buffer and method
Publication Date: 2010.07.15 MICRON TECHNOLOGY INC
  • US20100177571A1 patent drawing
  • US20100177571A1 patent drawing
  • US20100177571A1 patent drawing

AI summary

A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.