3D Memory Common Source Line Segmentation With Isolation Pillars

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving high element density and small size while maintaining storage capacity, as existing structures are prone to issues like wiggling or bending of common source lines during manufacturing processes.

Innovation Solution

The introduction of isolation pillars that interpose and separate segments of the common source lines, reducing their length and stabilizing the structure, along with the use of materials like silicon oxide or carbon-doped silicon for the pillars and spacers, and the formation of metal plugs and gate structures to enhance connectivity and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the common source line is made longer to connect memory cells, then the connectivity is improved, but the line becomes prone to wiggling or bending during manufacturing

Engineering Contradiction:
Improveconnectivity stabilityVSAvoidline shape stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The common source line is divided into multiple segments by introducing isolation pillars that physically separate the line into discrete sections. This segmentation prevents the entire line from bending or wiggling as a single continuous structure, while each segment maintains its electrical connectivity function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation pillars are introduced as intermediary structures between segments of the common source line. These pillars serve as both physical supports that prevent bending and as electrical isolators, mediating between the need for connectivity and the need for structural stability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If the memory device is designed with higher element density, then the storage capacity is improved, but the device size requirement becomes more challenging

Engineering Contradiction:
Improveelement densityVSAvoiddevice size
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional planar arrangement to a three-dimensional structure by vertically stacking multiple memory cell layers. This dimensional change allows significantly higher element density within a smaller footprint area, as memory cells are arranged in multiple levels rather than a single plane.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple memory cell structures are nested vertically one above another, with each layer containing complete memory cells. This nested arrangement maximizes the use of vertical space, enabling high-density storage without proportionally increasing the device footprint.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Stability of the object's composition

If the common source line is segmented into multiple parts, then the structural stability is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improveline structure stabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The isolation pillars serve multiple functions simultaneously: they act as physical supports to prevent line bending, as electrical isolators to separate line segments, and as structural anchors for the common source line. This multi-functionality reduces the need for additional separate components, simplifying the overall manufacturing process despite the segmentation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230269938A1Semiconductor structure and method of fabricating the same
Publication Date: 2023.08.24 MACRONIX INTERNATIONAL CO LTD
  • US20230269938A1 patent drawing
  • US20230269938A1 patent drawing
  • US20230269938A1 patent drawing

AI summary

A semiconductor structure includes a substrate, a common source plane disposed on the substrate, a plurality of memory cells vertically disposed on the substrate and electrically connected to the common source plane, a common source line disposed on the substrate and electrically connected to the common source plane, and an isolation pillar. The common source line extends along a first direction and has a first segment and a second segment. The isolation pillar interposes the first segment and the second segment of the common source line.