Memory Access Line Oxidation for Level-Based Resistivity Tuning
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Solution Overview
Problem
Existing memory devices face challenges in configuring access lines within multi-level memory arrays to achieve optimal resistivity, which affects the performance and longevity of far and near memory cells due to varying electrical distances and parasitic capacitances, while maintaining uniform fabrication processes.
Innovation Solution
The solution involves oxidizing access lines at different levels of the memory array to varying extents, using wet or dry techniques, to adjust their resistivity independently, ensuring that access lines at higher levels have lower resistivity than those at lower levels, thereby compensating for increased electrical distances from drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access lines at higher levels are made with lower resistivity to compensate for increased electrical distance from drivers, then performance of far memory cells is improved, but fabrication process complexity increases due to varying oxidation extents required
Solution Approach 1:
The patent applies local quality by making different portions of access lines have different resistivity characteristics. Specifically, access lines at higher levels are oxidized to a lesser extent than those at lower levels, creating localized variations in resistivity that match the electrical distance requirements of different memory cell regions. This allows far memory cells to receive adequate drive current while near memory cells are protected from excessive current spikes.
Solution Approach 2:
The patent changes the resistivity parameter of access lines by controlling the oxidation extent during fabrication. By adjusting oxidation parameters (such as oxidation time, temperature, or chemical concentration) for different access line levels, the patent creates a gradient of resistivity values that optimizes performance across the three-dimensional memory array without requiring fundamentally different fabrication processes.
2Duration of action of stationary object
If access lines at lower levels are made with higher resistivity to mitigate current spikes in near memory cells, then lifespan of near memory cells is prolonged, but drive current requirements for far memory cells increase
Solution Approach 1:
The patent implements local quality by assigning different resistivity characteristics to access lines based on their spatial location and function. Access lines serving near memory cells are oxidized to a greater extent, creating higher local resistivity that limits current spikes and extends cell lifespan. Conversely, access lines serving far memory cells are oxidized less, maintaining lower resistivity to ensure adequate signal strength over longer electrical distances.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying the oxidation extent parameter across different access line levels. This creates a controlled resistivity gradient where lower-level access lines (serving near cells) have higher resistivity and upper-level access lines (serving far cells) have lower resistivity, thereby simultaneously protecting near cells from current spikes and maintaining drive capability for far cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of memory devices by reducing drive current requirements for far cells and mitigating current spikes in near cells, thereby prolonging their lifespan and maintaining uniform fabrication processes.
Implementation Method 1
the first set of access lines are oxidized to a first extent... the second set of access lines are oxidized to a second extent
Data Source
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AI summary
Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.