Memory Dielectric Structure With Segmented Liner for CMP Stress

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Solution Overview

Problem

The etching process in memory devices faces the loading effect, leading to inconsistent contours of dielectric layers at the center and edges of the array area, causing excessive stress during chemical mechanical polishing and potential cracks in active areas, which affects the yield of the process.

Innovation Solution

A memory device design with a discontinuously embedded liner layer in the dielectric structure, featuring segments that act as polishing stop layers to reduce stress and prevent cracks by removing step heights during chemical mechanical polishing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the etching process is used to form dielectric layers, then the integration density of memory devices is improved, but the loading effect causes inconsistent contours at the center and edges of the array area, leading to excessive stress during chemical mechanical polishing

Engineering Contradiction:

Improvecontour consistencyVSAvoidpolishing stress

Core Design Contradiction:

Manufacturing precisionVSStress or pressure

Solution Approach 1:

The liner layer is divided into multiple discontinuous segments positioned at specific locations within the dielectric structure. These segments act as localized polishing stop layers that prevent excessive stress concentration during chemical mechanical polishing, thereby resolving the contour inconsistency and stress distribution problem caused by the loading effect in etching processes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the dielectric structure are provided with different liner layer configurations - continuous liner in some areas and discontinuous segments in other areas. This local differentiation allows the structure to withstand varying stress conditions during polishing, addressing the contour variation between center and edge regions of the array area.

Inventive Principle:

Principle #3Local quality

2Shape

If the chemical mechanical polishing process is applied to planarize the dielectric layers, then the surface flatness is improved, but the excessive stress causes cracks in active areas, affecting the yield of the process

Engineering Contradiction:

Improvesurface flatnessVSAvoidprocess yield

Core Design Contradiction:

ShapeVSReliability

Solution Approach 1:

The discontinuous liner layer segments are embedded in the dielectric structure before the chemical mechanical polishing process. These segments serve as pre-positioned cushioning elements that absorb and distribute polishing stress, preventing stress concentration that would lead to cracks in active areas, thus maintaining both surface flatness and process yield.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The liner layer segments act as intermediary elements between the polishing interface and the underlying active areas. They mediate the stress transfer during chemical mechanical polishing, reducing the direct stress impact on active areas while still enabling effective planarization of the dielectric surface.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If the self-aligning double patterning method is used to overcome optical limits, then the integration density is improved, but the pattern density variation between center and edges causes loading effect and contour inconsistency

Engineering Contradiction:

Improveintegration densityVSAvoidpattern uniformity

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The liner layer is configured with different continuity patterns in different regions of the dielectric structure - discontinuous segments in areas prone to loading effects and continuous liner in other areas. This local quality differentiation compensates for the pattern density variation between center and edge regions, maintaining contour uniformity across the entire array area while preserving high integration density achieved through SADP.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250318116A1Memory device and method of fabricating semiconductor device

Publication Date: 2025.10.09 WINBOND ELECTRONICS CORP

AI summary

A memory device, including first stacked structures, second stacked structures, a dielectric structure, and a liner layer located on a substrate. A first opening is located between the first stacked structures. A second opening is located between the second stacked structures. The dielectric structure covers the first stacked structures and the second stacked structures and is filled in the second opening. The dielectric structure includes a first portion covering the first stacked structures and a second portion covering the second stacked structures. The liner layer is discontinuously embedded in the dielectric structure. The liner layer includes a first segment and a second segment. The first segment is embedded in the first portion of the dielectric structure. The second segment is embedded in the dielectric structure in the second opening. The first segment and the second segment are separated by the second portion of the dielectric structure.