Memory Link ECC Without Wider I/O or Longer Bursts
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Solution Overview
Problem
Conventional memory systems face performance and cost issues due to the need for additional memory devices and increased I/O width for error correction codes (ECC), which also result in higher power consumption and reduced memory bandwidth.
Innovation Solution
Incorporating ECC encoding and decoding capabilities into both host and memory devices, allowing for error detection and correction without requiring additional memory devices, maintaining the same link configuration and burst length, and utilizing existing signal lines for ECC transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional memory devices are used for ECC storage, then memory link reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges ECC functionality into the existing memory device by adding an ECC encoder and decoder to the memory controller, eliminating the need for separate ECC storage devices. The ECC data is stored within the same memory array alongside regular data, combining multiple functions into a unified structure.
Solution Approach 2:
The memory device is designed to perform multiple functions: storing both regular data and ECC data within the same memory array, and the memory controller handles both data operations and ECC operations. This multi-functional approach eliminates the need for dedicated ECC hardware components.
2Reliability
If I/O width is increased to accommodate ECC, then memory link reliability is improved, but power consumption and PCB area increase
Solution Approach 1:
The patent combines ECC data transmission with regular data transmission by interleving ECC bits within the same data bus cycles. The same DQ lines and clock signals are used for both data and ECC, eliminating the need for additional I/O paths and reducing power consumption compared to separate ECC channels.
3Reliability
If I/O width is increased to accommodate ECC, then memory link reliability is improved, but PCB area and manufacturing cost increase
Solution Approach 1:
The patent merges ECC signaling into the existing memory interface by using the same DQ lines, address lines, and control signals for both data and ECC transmission. This approach requires no additional PCB traces or routing, maintaining the original PCB layout and reducing manufacturing complexity.
4Reliability
If data burst length is extended to transfer ECC bits, then memory link reliability is improved, but memory bandwidth and productivity decrease
Solution Approach 1:
The patent maintains continuous useful action by transmitting ECC bits during the same burst cycles as regular data, rather than extending burst length. The memory interface continuously transfers both data and ECC in parallel without idle cycles, maximizing bandwidth utilization while providing error correction.
Data Source
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AI summary
Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the burst length.