Memory Link ECC and Data Masking Parallel Write Path
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Solution Overview
Problem
As memory device capacity increases, it becomes difficult to fabricate memory devices without defective memory cells, and existing methods for correcting errors in channel transmission between a memory controller and a memory device lengthen write latency due to sequential performance of error correction and data masking operations.
Innovation Solution
A memory device is designed to perform link error correction, data masking, and data bus inversion operations in parallel, utilizing a syndrome calculator, error corrector, and data mask calculation circuit to generate error location signals and DM signals, minimizing write latency by simultaneous execution of these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction and data masking operations are performed sequentially, then transmission accuracy is improved, but write latency increases
Solution Approach 1:
The patent merges the error correction operation and data masking operation into a single parallel processing stage. The syndrome calculator, error corrector, and data mask calculation circuit operate simultaneously on the same input data, combining two previously sequential operations into one concurrent process, thereby reducing write latency while maintaining transmission accuracy
Solution Approach 2:
The data mask calculation circuit performs preliminary calculation of the DM signal based on the input data and error location signal before the error correction is complete. This preliminary action allows the masking operation to be ready in advance, enabling parallel execution and reducing the overall write latency without compromising the accuracy of error correction
2Quantity of substance
If memory device capacity increases, then storage capability is improved, but fabrication difficulty increases due to defective memory cells
Solution Approach 1:
The patent implements self-service through automatic defect detection and correction mechanisms. The syndrome calculator automatically identifies defective memory cells through error detection codes, and the error corrector automatically repairs the errors without requiring manual intervention or device replacement, enabling high-capacity devices to be manufactured with acceptable yield
Solution Approach 2:
The patent uses feedback mechanisms where error detection codes are calculated from the stored data and compared with received codes. When discrepancies are detected, the system generates error location signals that feed back into the correction process, allowing continuous monitoring and correction of fabrication defects in high-capacity memory devices
Data Source
AI summary
A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.