Memory Link Error Detection and Retry for High-Speed Data Transfer
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Solution Overview
Problem
Conventional memory systems face challenges in maintaining low bit-error rates (BER) as data rates increase, due to signaling and circuit limitations, which can lead to reliability issues and higher costs in developing faster interfaces with reduced complexity and increased noise.
Innovation Solution
A memory system with error detection and retry modes of operation, incorporating a memory controller that dynamically adds error detection and correction codes to data, and performs retry remedial actions when errors are detected, allowing for improved data transmission rates with lower error rates through error protection and retransmission mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission rate is increased to achieve higher bandwidth, then productivity is improved, but bit-error rate increases due to signaling limitations and noise
Solution Approach 1:
The patent applies preliminary action by proactively adding error detection codes (EDC) and error correction codes (ECC) to data packets before transmission. The memory controller pre-processes data with error protection mechanisms, so that when errors occur during high-speed transmission, they can be detected and corrected without retransmission, thus maintaining high data rates while ensuring reliability
Solution Approach 2:
The patent implements feedback through acknowledgment (ACK) and negative acknowledgment (NACK) signals. The memory device sends ACK to confirm successful reception of data packets, or NACK to request retransmission when errors are detected. This feedback mechanism ensures reliable data transmission while allowing the system to maintain high data rates by only retransmitting erroneous packets rather than all data
2Reliability
If conventional error protection methods are used to maintain low BER, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies segmentation by dividing error protection into two distinct layers: error detection codes (EDC) for detecting errors and error correction codes (ECC) for correcting errors. This segmentation allows the system to use simpler EDC for most packets and only invoke more complex ECC or retransmission mechanisms when actually needed, reducing average complexity while maintaining high reliability
Solution Approach 2:
The patent implements partial action by applying full error correction resources only when necessary. The system uses lightweight EDC for all transmissions, and only activates full ECC processing or retransmission protocols when EDC detects errors. This partial application of complex error protection mechanisms reduces overall computational complexity and resource usage while maintaining reliability
Data Source
AI summary
A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.