Memory Device Link Evaluation via Multi-Point Sampling
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Solution Overview
Problem
Existing memory devices face challenges in accurately determining the logic state of signals due to channel deterioration, leading to potential data errors. Current techniques are reactive and do not proactively assess the margin of error in the channel before errors occur.
Innovation Solution
A method is described where a memory device samples signaling at multiple reference points in the time and voltage domain to determine a candidate sequence of logic values. By comparing this sequence to the original sequence, the memory device can calculate the margin of error associated with the channel, allowing for proactive calibration to prevent data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory device uses a single reference point for sampling signals, then the device complexity is reduced, but the measurement precision of logic state determination deteriorates due to channel deterioration
Solution Approach 1:
The patent segments the sampling process by using multiple reference points (first reference point and second reference point) instead of a single reference point. Each reference point samples the signal at different time instances, allowing the system to capture channel variations and determine logic states more accurately despite channel deterioration.
Solution Approach 2:
The patent implements dynamic sampling by adjusting the reference point timing based on detected logic states. The sampler dynamically modifies the timing of subsequent samples according to the detected pattern, adapting to channel conditions and maintaining measurement precision even as the channel deteriorates over time.
2Reliability
If the memory device proactively evaluates the channel using multiple reference points and compares sequences, then the reliability of data transmission is improved, but the loss of time increases due to additional sampling and comparison operations
Solution Approach 1:
The patent performs preliminary channel evaluation by proactively sending test sequences through the channel before actual data transmission. This preliminary action characterizes the channel conditions in advance, allowing the system to adjust sampling parameters and timing to optimize both reliability and speed for subsequent data transmission.
Solution Approach 2:
The patent implements feedback mechanisms where the memory device compares the received sequence with the transmitted sequence, detects errors, and uses this information to adjust future sampling operations. The feedback loop continuously optimizes the sampling process, improving reliability while minimizing time loss through adaptive parameter adjustment.
Data Source
AI summary
Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.