Memory Link Timing Calibration for High-Bandwidth Flash Transfer
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Solution Overview
Problem
Non-volatile flash memory systems face complexity, high cost, and incompatibility with modern interface attributes due to the need for a large number of communication links with high bandwidth, which complicates the memory system design.
Innovation Solution
A protocol involving a shared, high-swing command/address link and point-to-point low-swing data links with timing calibration operations, using phase-locked loops (PLL) or delay-locked loops (DLL) to facilitate high-bandwidth data transfers to multiple memory devices, optimizing power usage by enabling power sources only when needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of communication links with high bandwidth are provided to multiple non-volatile memory devices, then data transfer capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges command and address signals onto a single shared link, combining multiple signal types into one communication channel. This reduces the total number of links needed while maintaining the ability to communicate with multiple memory devices, thereby reducing system complexity while preserving data transfer capability.
Solution Approach 2:
The patent segments the communication protocol into distinct phases (command phase, address phase, data phase) with different signaling characteristics. By time-multiplexing different signal types on the same link, the system achieves high bandwidth for data transfers while using a simpler shared infrastructure for control signals.
2Productivity
If a large number of communication links with high bandwidth are provided to multiple non-volatile memory devices, then data transfer capability is improved, but manufacturing cost increases
Solution Approach 1:
By merging command/address signaling and data transfer on fewer physical links rather than providing dedicated high-bandwidth links for each device, the patent reduces the total component count and interconnect complexity, leading to lower manufacturing costs while maintaining high data transfer capability.
3Productivity
If a large number of communication links with high bandwidth are provided to multiple non-volatile memory devices, then data transfer capability is improved, but compatibility with modern flash memory interfaces is worsened
Solution Approach 1:
The patent employs dynamic signaling modes where the same physical link can operate in different modes (command mode with large-swing signals, data mode with low-swing signals). This dynamic adaptability allows the interface to be compatible with modern flash memory core attributes while maintaining high bandwidth data transfer capability.
Solution Approach 2:
The patent changes signal parameters (swing amplitude, timing) based on the operational mode. Large-swing signals for command/address compatibility with modern flash interfaces, and low-swing signals for high-speed data transfers, allowing the same infrastructure to serve both compatibility and performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the system design, reduces costs, and enhances compatibility with modern flash memory interfaces by enabling efficient, high-bandwidth data transfers while minimizing power consumption.
Implementation Method 1
timing calibration operations, using phase-locked loops (PLL) or delay-locked loops (DLL) to facilitate high-bandwidth data transfers
Data Source
AI summary
The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.