Dual-Mode Memory Links for High-Speed Access and Signal Quality
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face limitations in high-speed operations due to signal quality degradation at high frequencies, particularly in parallel interfaces, which affects their performance in future electronic devices requiring high data rates, such as mobile multimedia devices recording high-definition moving pictures.
Innovation Solution
A dual-mode memory system with interface circuitry that can switch between serial and parallel modes, allowing each link to operate independently in serial mode and collectively in parallel mode, using a single set of input and output controls for all links during parallel mode, and employing link and bank controllers to manage read and write operations effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel interface is used for high-speed memory operations, then data transfer rate is improved, but signal quality deteriorates due to cross-talk, signal skew and attenuation
Solution Approach 1:
The memory interface is designed to dynamically switch between parallel and serial modes based on operational requirements. The interface circuitry can reconfigure the data paths to use parallel configuration for high-speed operations when signal quality is maintained, and switch to serial configuration when signal degradation occurs, thus adapting to changing conditions to resolve the contradiction between speed and reliability
Solution Approach 2:
The system changes the operational parameters of the interface by switching between parallel and serial modes. In parallel mode, multiple data lines operate simultaneously for high throughput; in serial mode, data is transmitted bit-by-bit through fewer lines, reducing cross-talk and signal skew. This parameter change allows the system to optimize for either speed or signal quality depending on the specific operational context
2Reliability
If serial mode is used for memory operations, then signal quality is maintained, but data transfer rate decreases
Solution Approach 1:
The memory interface dynamically selects between serial and parallel modes based on real-time conditions. When high signal quality is prioritized (e.g., during critical data transfers or when operating at lower frequencies), the interface switches to serial mode. When maximum throughput is needed and signal integrity is maintained, it switches to parallel mode, thus resolving the trade-off between reliability and productivity
3Quantity of substance
If multiple memory devices are connected in multi-drop configuration, then device density is increased, but delay time increases due to loading effect
Solution Approach 1:
The multi-drop configuration is segmented into multiple serial daisy-chain connections. Instead of connecting all memory devices to a single shared bus (multi-drop), each device is connected in sequence to the previous one, creating individual serial pathways. This segmentation reduces the loading effect on any single connection, thereby reducing delay time while still allowing multiple devices to be connected in the system
Data Source
AI summary
Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.