Memory Read Decoding With LLR Re-Conversion and Voltage Tracking
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Solution Overview
Problem
Current memory systems face challenges in efficiently correcting errors in data read from memory devices due to variations in cell transistor properties, leading to inaccurate determination of stored data states and reduced error correction capabilities.
Innovation Solution
The memory system employs an ECC circuit with a controller that uses LLR tables to convert hard-bit and soft-bit data into LLR values, enabling error correction through BCH and LDPC decoding, and adjusts read voltages based on Vth tracking to improve decoding success rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used, then error correction is performed, but the time required for successful error correction is excessive and decoding success rate is reduced
Solution Approach 1:
The patent performs preliminary actions by acquiring multiple types of data (hard-bit data, soft-bit data, and refined soft-bit data) and converting them to LLR values before actual decoding. This preliminary preparation of multiple LLR value sets enables faster retry operations without requiring additional data acquisition time, thus reducing the overall error correction time while maintaining high decoding success rates
Solution Approach 2:
The patent changes parameters by converting the same physical data (charge trap layer states) into multiple different parameter representations (LLR values) through different conversion relationships. This allows the system to try different decoding approaches with the same data, improving decoding success rate without requiring additional time for data acquisition
2Measurement precision
If multiple data readings are performed to improve decoding success rate, then error correction accuracy is improved, but the time required for data acquisition increases
Solution Approach 1:
The patent performs preliminary action by acquiring hard-bit data, soft-bit data, and refined soft-bit data in advance and converting them to LLR values before decoding is needed. This preliminary data preparation ensures high measurement precision is achieved upfront, and subsequent decoding retries can proceed without additional data acquisition time
Solution Approach 2:
The patent creates multiple copies of data representations (different LLR values from the same physical data) instead of acquiring multiple physical readings. The hard-bit data, soft-bit data, and refined soft-bit data are all copies derived from the same charge trap layer states, providing multiple decoding opportunities without additional acquisition time
Data Source
AI summary
In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.