3D Memory Local-Line Contacts With Stepped Stack Connection Layout
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Solution Overview
Problem
Current semiconductor memory devices, particularly three-dimensional flash memory devices, face challenges in efficiently connecting local lines to peripheral circuits, which affects data storage and retrieval speeds and integration density.
Innovation Solution
A semiconductor memory device with a stacked structure of conductive layers in a step configuration and contact plugs with protrusion parts that penetrate the slimming region, allowing for improved electrical connections between memory blocks and peripheral circuits, and a manufacturing method involving alternate stacking of material layers, sacrificial layer removal, and conductive material filling to form these connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to penetrate through the entire stacked structure, then electrical connection is achieved, but manufacturing complexity and difficulty increase due to the need to pass through multiple conductive layers and insulating layers
Solution Approach 1:
The contact plug formation process is segmented into multiple stages: first forming contact plugs that penetrate only the insulating layer to reach the conductive layer, then separately forming connection holes through the conductive layer to reach the local line. This segmentation avoids the complexity of forming single deep holes through the entire stacked structure, reducing manufacturing difficulty while maintaining reliable electrical connection.
Solution Approach 2:
The conductive layers are pre-formed in a step structure with different heights in different regions before contact plug formation. This preliminary action creates natural stopping points and facilitates the segmented contact plug formation process, making manufacturing easier while ensuring proper electrical connections to the local lines.
2Quantity of substance
If conductive layers are stacked densely to increase integration density, then storage capacity improves, but connection reliability to peripheral circuits deteriorates due to reduced space for contact plugs
Solution Approach 1:
The conductive layers are formed with different heights in different regions (step structure), creating local variations in the stacked structure. This allows contact plugs to connect to conductive layers at optimal locations while maintaining high integration density in other areas, thus preserving both connection reliability and storage capacity.
Solution Approach 2:
The invention utilizes vertical dimension variations through the step structure of conductive layers at different heights. This dimensional approach allows multiple connection points to be achieved within the same planar footprint, maintaining high integration density while ensuring reliable connections through properly positioned contact plugs.
3Quantity of substance
If the stacked structure is made taller to increase storage capacity, then integration density improves, but manufacturing precision requirements worsen due to increased depth of contact holes
Solution Approach 1:
The contact formation process is divided into segmented steps: first forming contact plugs to a first depth reaching the conductive layer, then forming additional connection holes to a second depth to reach the local line. This segmentation reduces the required precision for each individual hole formation step compared to forming a single deep hole through the entire structure.
Solution Approach 2:
The conductive layers are pre-formed with a step structure that creates natural reference levels. This preliminary action establishes stopping points that guide the contact plug formation process, reducing the need for extremely precise depth control in subsequent manufacturing steps while maintaining tall overall structure for high storage capacity.
Data Source
AI summary
A semiconductor memory device, and a method of manufacturing a semiconductor memory device, includes a stacked structure including a plurality of conductive layers for local lines stacked on a semiconductor substrate defined by a cell region and a slimming region to be spaced apart from each other, wherein the plurality of conductive layers for local lines are stacked in a step structure in the slimming region. The semiconductor memory device also includes a plurality of contact plugs formed to penetrate the stack structure in the slimming region, the plurality of contact plugs corresponding to each of the conductive layers for local lines. Each of the plurality of contact plugs includes a protrusion part protruding horizontally, and the protrusion part is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines.