Semiconductor Memory Device With Localized Error Tolerance
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Solution Overview
Problem
Conventional memory systems incur high ECC costs and increased error risks due to noise sensitivity when storing multi-level data, particularly in deep learning applications where bit reliability is uniformly controlled, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A semiconductor memory device design that allows errors in lower significant bits, utilizing a sense amplifier for unary read operations and reducing ECC costs by allowing data errors within a certain range, specifically using a multi-level memory cell array and a sense amplifier with a clock counter to efficiently read and write data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform reliability control is applied to all bits in multi-level memory, then data reliability is maintained, but ECC cost increases and noise sensitivity increases
Solution Approach 1:
The patent applies different reliability control strategies to different bits based on their significance. Upper significant bits are protected with higher reliability requirements while lower significant bits allow controlled errors. This local differentiation reduces ECC overhead while maintaining data quality where it matters most.
Solution Approach 2:
The patent changes the reliability parameter dynamically based on bit position and data type. For deep learning weight data, upper bits maintain strict reliability while lower bits tolerate errors. This parameter adaptation reduces the overall ECC burden while preserving critical information.
2Reliability
If uniform reliability control is applied to all bits, then data consistency is maintained, but noise sensitivity increases leading to more errors
Solution Approach 1:
The patent implements local quality control by applying different error tolerance levels to different bit positions. Upper significant bits use strict error correction while lower significant bits use relaxed control, reducing overall noise sensitivity impact.
Solution Approach 2:
The patent converts the harmful effect of noise on lower significant bits into an acceptable trade-off. By allowing controlled errors in less critical lower bits, the system reduces the amplification of noise effects that would occur with uniform strict control across all bits.
3Quantity of substance
If multi-level memory is used to store more data per cell, then storage density increases, but reading accuracy decreases due to noise
Solution Approach 1:
The patent applies local quality control by differentiating between upper and lower significant bits during read operations. Upper bits receive higher precision reading with stricter error thresholds, while lower bits use relaxed reading with higher tolerance, optimizing the balance between storage density and reading accuracy.
4Reliability
If deep learning data is stored with uniform bit reliability, then data integrity is maintained, but efficiency decreases due to excessive ECC overhead
Solution Approach 1:
The patent changes the reliability parameter based on data type and bit position. For deep learning weight data, upper significant bits maintain strict integrity control while lower bits use relaxed control, reducing ECC overhead and improving storage efficiency while preserving critical data quality.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory, a controller, and a sense amplifier. The memory includes a plurality of memory cells, wherein each of the memory cells can store a multi level indicating one data. The controller writes the multi level to one cell of the memory. The sense amplifier performs unary read of data from the multi level written in the one cell. The data is data in which an error of a predetermined lower significant bit is allowed. The controller reads data indicated by the multi level stored in the one cell of the memory from the sense amplifier.