Memory Address Locking for Offloaded Instruction Ordering
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Solution Overview
Problem
Conventional memory fences or barriers are insufficient in preserving memory ordering between offloaded instructions and younger non-offloaded instructions, particularly in architectures where offload instructions retire at the CPU core before they pass a global synchronization point, leading to potential issues with stale data access and incorrect execution.
Innovation Solution
Implement hardware and instruction set architecture support in CPU cores, caches, and functional logic blocks to enforce memory ordering between offloaded and non-offloaded instructions, using locks on memory addresses and synchronization primitives to ensure exclusive access and correct ordering, including address lock buffers and synchronization primitives like barrier_start and barrier_end instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If offload instructions are allowed to retire at the CPU core before passing a global synchronization point, then processing speed is improved, but memory ordering between offloaded and non-offloaded instructions cannot be preserved
Solution Approach 1:
The system performs preliminary actions by placing locks on memory addresses before offload instructions complete execution. The lock placement occurs when the offload instruction retires at the CPU core, preemptively preventing younger non-offloaded instructions from accessing the memory address before the offload operation completes and cache operations finish.
Solution Approach 2:
Locks serve as an intermediary mechanism between offload instructions and younger non-offloaded instructions. The lock buffer acts as a mediator that tracks which memory addresses are currently being accessed by offload operations and blocks younger instructions from accessing those same addresses, thereby preserving memory ordering without requiring a global synchronization point.
2Reliability
If conventional memory fences or barriers are used to preserve memory ordering, then memory ordering is maintained, but processing performance deteriorates due to blocking younger instructions
Solution Approach 1:
Instead of using a global memory fence or barrier that blocks all younger instructions, the system applies locking locally to specific memory addresses that are currently being accessed by offload operations. This selective approach preserves memory ordering only where necessary, allowing younger instructions to continue executing on other memory addresses and maintaining overall processing performance.
Solution Approach 2:
The system places locks on memory addresses in advance when offload instructions retire, before the actual cache operations complete. This preliminary locking prevents the need for later blocking mechanisms, allowing the system to maintain memory ordering without requiring global synchronization that would block processing.
3Reliability
If locks are placed on memory addresses to prevent stale data access, then data correctness is improved, but device complexity increases due to lock buffer management
Solution Approach 1:
The lock buffer automatically manages locks based on offload instruction retirement and cache operation completion. The system self-services by tracking which memory addresses require locking and when locks should be released, eliminating the need for complex manual lock management or additional synchronization hardware.
Data Source
AI summary
Preserving memory ordering between offloaded instructions and non-offloaded instructions is disclosed. An offload instruction for an operation to be offloaded is processed and a lock is placed on a memory address associated with the offload instruction. In response to completing a cache operation targeting the memory address, the lock on the memory address is removed. For multithreaded applications, upon determining that a plurality of processor cores have each begun executing a sequence of offload instructions, the execution of non-offload instructions that are younger than any of the offload instructions is restricted. In response to determining that each processor core has completed executing its sequence of offload instructions, the restriction is removed. The remote device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.