Memory Array Lockout Segmentation for PIC Data Loss Control
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Solution Overview
Problem
Flash memory devices experience unnecessary data loss due to lockout operations being performed in units of chips during Plane Independent Core (PIC) operations, leading to inefficient data management and potential data loss during Sudden-Power Off or voltage fluctuations.
Innovation Solution
A memory device design where each Memory Array Tile (MAT) has its own local lockout circuit, allowing for independent operation and voltage management, reducing unnecessary data loss by determining whether to lock out based on individual MAT conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lockout circuit is implemented at chip level, then operation protection is improved, but data loss increases during PIC operations
Solution Approach 1:
The lockout circuit is divided into multiple independent instances, with each MAT (Memory Array Tile) having its own dedicated lockout circuit. This segmentation allows each MAT to independently manage its own lockout state, preventing unnecessary data loss in other MATs when one MAT experiences voltage fluctuations or power disruptions during PIC operations.
2Stability of the object's composition
If lockout is performed in units of chips, then operation stability is improved, but productivity decreases due to unnecessary data loss
Solution Approach 1:
The memory device is segmented into multiple independent MATs, each with its own lockout circuit and voltage management. This allows stable operation protection at the MAT level rather than chip level, enabling other MATs to continue operating normally and improving overall data management efficiency during PIC operations.
3Loss of information
If individual MAT operation is enabled, then data loss is reduced, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple MATs with independent lockout circuits, allowing individual MAT operation and reducing data loss.
Solution Approach 2:
Each MAT is designed with universal functionality to perform program, read, and erase operations independently. The identical structure of multiple MATs with the same lockout circuit design simplifies the overall system architecture while enabling individual operation, as each MAT can function autonomously with the same circuit configuration.
Data Source
AI summary
A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.