3D Memory Array and Control Logic Stacking for Higher Density
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Solution Overview
Problem
Microelectronic device designs face challenges in increasing integration density and performance due to limitations in the configuration and performance of control logic devices within memory devices, which consume more space and hinder reductions in size and improvements in speed and power efficiency.
Innovation Solution
The method involves forming a microelectronic device by separately creating a first microelectronic device structure with vertical stacks of memory cells and a second microelectronic device structure with control logic devices, then attaching them with oxide bonding, and replacing sacrificial structures with conductive material to establish electrical connections, facilitating shorter connections and improved data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control logic devices are integrated within the memory device structure, then control operations can be performed, but the device consumes more real estate and the memory density is reduced
Solution Approach 1:
The memory device is divided into two separate structures: a first microelectronic device structure containing the memory array, and a second microelectronic device structure containing the control logic devices. These structures are formed independently and then attached together, allowing each to be optimized for its specific function without compromising the other's performance or size.
2Ease of manufacture
If control logic devices are formed over the base control logic structure using standard processing conditions, then the memory array can be integrated, but the control logic device configurations and performance are limited
Solution Approach 1:
By separating the control logic devices into a distinct second microelectronic device structure that is formed independently, the patent enables the use of optimized processing conditions specifically tailored for control logic devices, rather than being constrained by the memory array's processing requirements.
3Productivity
If the quantity and complexity of control logic devices are increased to handle higher memory array density, then more control operations can be performed, but the device size increases and performance is impeded
Solution Approach 1:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture by attaching the second microelectronic device structure (control logic) to the first microelectronic device structure (memory array). This vertical stacking reduces the horizontal footprint and shortens the connection distances between control logic devices and memory cells, thereby improving speed and performance while maintaining high control operation capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory device performance by reducing real estate consumption, improving data transfer speeds, and lowering power consumption while maintaining high integration density.
Implementation Method 1
attaching them with oxide bonding
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures.