3D Memory-Logic Bonding for Compact DRAM Control Layouts
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM devices, due to processing conditions and the configuration of control logic devices, which limit the reduction of feature size and performance enhancements like faster speed and lower power consumption.
Innovation Solution
The method involves forming microelectronic devices with array regions, digit line exit regions, word line exit regions, and socket regions, using conductive and insulative materials, and specific structures like contact structures and routing tiers to optimize the arrangement and performance of control logic devices within the device architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing conditions (temperatures, pressures, materials) are used for forming the memory array over the base control logic structure, then the memory array can be formed, but the configurations and performance of the control logic devices are limited
Solution Approach 1:
The device is divided into two separate structures: a base control logic structure formed first, and a memory array structure formed separately and then attached to the base structure. This segmentation allows each structure to be optimized independently under their respective processing conditions, resolving the contradiction between forming the memory array and maintaining control logic device performance.
Solution Approach 2:
The invention transitions from a planar integration approach to a three-dimensional stacked architecture where the memory array is vertically attached to the base control logic structure. This dimensional change enables independent optimization of each layer while achieving high-density integration.
2Productivity
If the quantities, dimensions, and arrangements of control logic devices are increased to control DRAM cells, then more DRAM cells can be controlled, but the horizontal footprint of the memory device increases
Solution Approach 1:
The control logic devices are arranged in a three-dimensional stacked configuration rather than a planar layout. Multiple control logic devices are vertically stacked above each other, enabling increased control capability for more DRAM cells while maintaining a compact horizontal footprint.
Solution Approach 2:
Control logic devices are nested vertically within a compact horizontal space. The stacked arrangement allows multiple control logic devices to occupy the same horizontal footprint area by stacking them in the vertical dimension, similar to nested dolls.
3Device complexity
If conventional control logic device arrangements are used, then the device structure is simple, but performance improvements like faster ON/OFF speed and lower power consumption are impeded
Solution Approach 1:
The control logic devices are arranged in a vertical stack with specific spatial relationships that enable improved performance. The three-dimensional arrangement optimizes signal paths and reduces interference, achieving faster ON/OFF speeds and lower power consumption compared to conventional planar arrangements.
Solution Approach 2:
The control logic devices in different vertical positions have optimized local configurations tailored to their specific functions. This local optimization of device characteristics and arrangements enables improved overall performance while maintaining manageable structural complexity.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.