Direct-Bonded Memory-on-Logic Dies for Thermal Process Separation
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Solution Overview
Problem
The integration of logic circuits and memory cells on a single substrate is hindered by temperature sensitivity, where high-temperature process steps damage low-temperature regime materials used in memory cells, restricting independent optimization of electrical characteristics and leading to adverse effects such as shortened charge retention and degraded performance.
Innovation Solution
A direct bonding scheme is employed to combine semiconductor dies fabricated in different temperature regimes, using conductive and dielectric materials like copper and silicon oxides, which are aligned and bonded, then annealed to form permanent metallurgical bonds, allowing for independent optimization of logic and memory cell processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic circuits and memory cells are integrated on a single substrate, then device functionality is improved, but high-temperature process steps damage low-temperature regime materials used in memory cells
Solution Approach 1:
The patent divides the semiconductor device into separate logic die and memory die, each fabricated independently in their respective temperature regimes. The logic die is processed at high temperatures suitable for transistor formation, while the memory die is processed at low temperatures to preserve sensitive materials like phase-change materials or magnetoresistive materials. These separate dies are then bonded together through a substrate, allowing each segment to be optimized for its specific temperature requirements while achieving integrated functionality.
2Area of stationary object
If separate semiconductor dies are stacked to reduce footprint, then area is reduced, but bond wires increase package height and signal propagation delays
Solution Approach 1:
The patent extracts and eliminates the bond wire interconnect layer from the package structure. Instead of using traditional bond wires to connect the logic die and memory die, the invention implements direct die-to-die bonding where the active surfaces of the dies are bonded together. This removes the intermediate bond wire layer, thereby reducing the overall package height while maintaining the stacked configuration for footprint reduction.
3Area of stationary object
If separate semiconductor dies are stacked, then footprint is reduced, but bond wires introduce signal propagation delays
Solution Approach 1:
The patent extracts and eliminates the bond wire interconnect layer from the package structure. Instead of using traditional bond wires to connect the logic die and memory die, the invention implements direct die-to-die bonding where the active surfaces of the dies are bonded together. This removes the intermediate bond wire layer, thereby reducing the overall package height while maintaining the stacked configuration for footprint reduction.
4Reliability
If high-temperature process steps are used for logic circuits, then logic circuit performance is improved, but memory cell charge retention is shortened
Solution Approach 1:
The patent divides the semiconductor device into separate logic die and memory die, each fabricated independently in their respective temperature regimes. The logic die is processed at high temperatures suitable for transistor formation, while the memory die is processed at low temperatures to preserve sensitive materials like phase-change materials or magnetoresistive materials. These separate dies are then bonded together through a substrate, allowing each segment to be optimized for its specific temperature requirements while achieving integrated functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of integrated semiconductor devices with improved performance by reducing signal propagation delays and enhancing form factors, enabling new applications and efficient data transfer between memory and logic components.
Implementation Method 1
annealed to form permanent metallurgical bonds
Implementation Method 2
annealed to form permanent metallurgical bonds
Data Source
AI summary
Semiconductor memory dies bonded to logic dies and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes a logic die and one or more memory dies directly bonded to the logic die. The logic die includes integrated circuits generated using relatively high temperature process steps whereas the memory dies include memory cells with materials generated using relatively low temperature process steps. The logic die and the memory dies have been separately fabricated in two different wafers such that process steps generating them can be optimized independently of each other. The resulting semiconductor device including the memory dies bonded to the logic die functions as a single device as if they were formed in a monolithic substrate. The resulting semiconductor device may be configured to perform artificial intelligence tasks.