Memory-Logic Die Routing via Wafer Bonding for Higher Bandwidth
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Solution Overview
Problem
Current memory devices face inefficiencies in data transfer between memory and logic dies, particularly when using global data buses, which can limit bandwidth and increase power consumption.
Innovation Solution
Implementing a wafer-on-wafer bonding process to directly couple memory and logic dies, allowing for high-bandwidth data transfer without the need for a global data bus, using a wide bus for efficient data routing between the memory and logic dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a global data bus is used for data transfer between memory die and logic die, then device complexity is reduced, but data bandwidth is limited and power consumption increases
Solution Approach 1:
The patent divides the data transfer path into multiple parallel channels by bonding multiple memory dies to multiple logic dies simultaneously. Each die pair forms an independent data transfer channel, eliminating the single global data bus bottleneck and enabling parallel data transmission across all channels.
Solution Approach 2:
The patent transitions from a two-dimensional global data bus architecture to a three-dimensional stacked architecture where memory dies are vertically bonded to logic dies. This vertical integration creates direct short-distance connections, adding a spatial dimension that eliminates the need for long horizontal data bus paths.
2Ease of operation
If a global data bus is used for data transfer, then ease of operation is maintained, but power consumption increases
Solution Approach 1:
The patent extracts data transfer operations from the centralized global data bus and distributes them to multiple independent direct connections between bonded die pairs. Each connection operates autonomously, eliminating the energy overhead of centralized bus arbitration and control mechanisms.
Solution Approach 2:
The wafer-on-wafer bonding process establishes all data transfer connections in advance during manufacturing, before the device operates. This preliminary configuration of direct physical connections eliminates the need for dynamic bus allocation and control during operation, reducing operational power consumption.
3Productivity
If wafer-on-wafer bonding is implemented to directly couple memory and logic dies, then data bandwidth increases significantly, but device complexity increases
Solution Approach 1:
The patent merges multiple memory dies with multiple logic dies in a single wafer-on-wafer bonding operation. This combines the benefits of multiple parallel data channels with a unified bonding process, achieving high bandwidth without proportionally increasing operational complexity since all connections are established simultaneously during manufacturing.
4Use of energy by moving object
If wafer-on-wafer bonding is used to create direct connections, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The wafer-on-wafer bonding process is designed to be self-aligning, where the bonding mechanism itself provides the precision alignment needed for direct die connections. This self-service approach to alignment reduces the need for external precision positioning systems and complex alignment procedures.
Data Source
AI summary
A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.