Memory-Logic Package Stacking for High-Bandwidth Interconnects
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Solution Overview
Problem
The integration of logic and DRAM dies in a single integrated circuit package faces challenges in maintaining a small form factor while achieving the high bandwidth required for data flow, as they are typically integrated into separate semiconductor dies.
Innovation Solution
The implementation of a redistribution layer with interconnects to couple a logic die to a stack of memory dies, either through laterally extending wire bonds or vertical metal pillars, and the use of through-mold vias to connect redistribution layers, allowing for high-bandwidth data transfer while maintaining a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic die and DRAM dies are integrated into separate semiconductor dies, then manufacturing flexibility and reliability are improved, but bandwidth and form factor are worsened
Solution Approach 1:
The patent transitions from traditional lateral packaging to a vertical stacking architecture where memory dies are stacked above the logic die. This dimensional change enables high bandwidth communication through short vertical interconnects (through-mold vias and redistribution layers) while maintaining separate dies for reliability, effectively resolving the contradiction between separate die reliability and data bandwidth requirements
2Productivity
If logic die and DRAM dies are packaged in a single integrated circuit package, then bandwidth is improved, but form factor and manufacturing complexity are worsened
Solution Approach 1:
By stacking memory dies vertically above the logic die rather than placing them side-by-side, the patent dramatically reduces the lateral footprint of the package. The vertical interconnects through the mold compound enable high bandwidth communication within a compact form factor, resolving the contradiction between bandwidth and package area
3Productivity
If vertical stacking is implemented with through-mold vias, then bandwidth is improved and form factor is reduced, but manufacturing precision and difficulty are worsened
Solution Approach 1:
The patent incorporates alignment features and registration marks during the die stacking process, and uses underfill material to compensate for thermal expansion differences. These preliminary actions address potential alignment issues before they occur during assembly, making the manufacturing process more robust despite the high precision requirements of through-mold vias
Data Source
AI summary
An integrated circuit package is provided in which a stack of memory dies couples to a redistribution layer through a plurality of wire bonds or metal pillars. The redistribution layer is configured to support the signaling between the memory dies and a logic die within the integrated circuit package.