Combined Memory Module Logic and PMIC for Lower-Power Bandwidth Scaling

The patent segments the memory system into separate functional components: memory devices, memory buffer devices, and logic buffer devices are divided into distinct semiconductor dies. This segmentation allows each component to be optimized independently for power efficiency while maintaining high integration benefits, resolving the contradiction between integration and power consumption.

The patent introduces an intermediary memory buffer device that sits between the memory devices and logic buffer devices. This intermediary component manages data flow and buffering operations separately, reducing power consumption by avoiding unnecessary data movements and enabling selective activation of buffer operations, thus maintaining integration benefits while reducing overall system power usage.

By segmenting the memory system into separate memory devices, memory buffer devices, and logic buffer devices on different semiconductor dies, the patent enables parallel data flow paths. Multiple memory devices can simultaneously access the memory buffer device, and multiple logic buffer devices can operate in parallel, significantly increasing memory system bandwidth while maintaining high integration.

The patent transitions from a two-dimensional integration approach (everything on one chip) to a three-dimensional stacked architecture using silicon interposers. This vertical stacking creates additional spatial dimensions for data flow, allowing simultaneous access paths and increasing bandwidth without sacrificing integration density.

The patent segments critical path operations into separate dedicated components: logic buffer devices handle command and address buffering separately from data buffer devices. This segmentation allows each component to be optimized for its specific function, reducing operational latency through specialized high-speed interfaces while maintaining manufacturing simplicity by using standard semiconductor fabrication processes for each die.

The patent introduces intermediary logic buffer devices that act as mediators between the host interface and memory devices. These intermediaries pre-process commands and addresses, performing preliminary actions that reduce the latency of memory operations while keeping the overall architecture manufacturable using established multi-chip module techniques.

The patent applies local quality by providing different voltage levels to different functional blocks within the memory system. High-speed logic buffer devices receive higher voltages for fast data transition, while memory buffer devices and memory devices operate at lower voltages for power efficiency. This localized voltage optimization achieves high speed where needed without proportionally increasing overall power consumption.

The patent implements dynamic voltage scaling through PMIC modules that can adjust supply voltages based on operational requirements. During high-performance modes, voltages are increased to boost data transition rates; during low-activity modes, voltages are reduced to minimize power consumption. This dynamic adjustment resolves the contradiction between speed and power by adapting to actual system needs.