Memory Logic Initialization via Shared Reset Pin Test Mode
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Solution Overview
Problem
Semiconductor memory devices face challenges in initializing internal logic circuits without a dedicated external reset pin, leading to difficulties in ensuring reliable operation and error detection under stable source voltage conditions.
Innovation Solution
A semiconductor memory device is designed with a power-up signal generating unit, an internal reset signal generating unit, and an internal logic initializing signal generating unit, which utilize an arbitrary external pin and test mode signals to initialize the internal logic circuit, allowing for error detection and correction without a dedicated external reset pin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated external reset pin is added to initialize internal logic circuits, then initialization reliability is improved, but device complexity increases
Solution Approach 1:
The patent reuses an existing external pin ( originally intended for other functions) to serve as a reset function pin, allowing the same pin to perform multiple functions including initialization. This eliminates the need for a dedicated reset pin while maintaining initialization capability, thus improving reliability without increasing device complexity.
2Reliability
If the power-up signal generating unit detects source voltage level to generate power-up signal, then internal logic circuits are initialized without latch-up problem, but it becomes difficult to determine whether initial operation is in fault when source voltage is stable
Solution Approach 1:
The patent introduces a test mode determining unit that acts as an intermediary to generate a test mode signal, which then enables the reset function pin to generate an internal reset signal. This intermediary mechanism allows differentiation between normal power-up initialization and test-mode initialization, enabling fault detection while maintaining latch-up prevention capabilities.
3Device complexity
If an extra initializing apparatus such as dedicated external reset pin is not included, then device complexity is reduced, but it becomes difficult to deal with errors occurring under stable source voltage state
Solution Approach 1:
The patent enables the existing external pin to serve itself with multiple functions including reset functionality when test mode is activated. The system uses its own existing resources (the external pin) to provide initialization and error handling capabilities without requiring additional dedicated components, thus maintaining low device complexity while improving error handling capability.
Data Source
AI summary
Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal.