Memory Logic Initialization Circuit Without a Dedicated Reset Pin
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Solution Overview
Problem
Semiconductor memory devices face challenges in initializing internal logic circuits without a dedicated external reset pin, leading to difficulties in ensuring reliable operation and error detection under stable source voltage conditions.
Innovation Solution
A semiconductor memory device is designed with a power-up signal generating unit, an internal reset signal generating unit, and an internal logic initializing signal generating unit, which utilize an arbitrary external pin and test mode signals to initialize internal logic circuits, allowing for error detection and correction without a dedicated external reset pin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a power-up signal generating unit is used to initialize internal logic circuits, then latch-up problems are prevented, but it becomes difficult to determine whether initial operation faults occur
Solution Approach 1:
The initialization function is segmented into two independent signal paths: power-up signal for latch-up prevention and reset signal for fault detection. This allows each signal to serve its specific purpose without interfering with the other, enabling both reliability and detectability.
Solution Approach 2:
A dedicated reset signal is introduced as an intermediary mechanism to bridge the gap between power-up initialization and fault detection. This reset signal acts as a mediator that can trigger initialization independently, allowing external observation and testing of initial operation faults.
2Difficulty of detecting and measuring
If a dedicated external reset pin is added for initialization, then fault detection becomes easier, but device complexity increases
Solution Approach 1:
An existing external pin is given multiple functions: it serves as both a data/address pin during normal operation and as a reset signal input during initialization. This multi-functionality eliminates the need for a dedicated reset pin while maintaining fault detection capability.
Solution Approach 2:
The reset function is merged with the existing external pin structure. The pin's normal functionality and reset functionality are combined into a single physical entity, reducing device complexity while achieving the desired fault detection capability.
3Device complexity
If internal logic circuits are initialized without a dedicated reset pin, then device complexity is reduced, but reliability under stable source voltage conditions deteriorates
Solution Approach 1:
The initialization system becomes dynamic by allowing the reset signal to be activated on-demand during stable voltage conditions. The system can transition between normal operation and initialization modes using the same external pin, providing flexibility without additional hardware.
Solution Approach 2:
The system uses its existing external pin infrastructure to provide reset functionality, making the system self-sufficient. No external dedicated reset pin is needed because the existing pin structure can serve the reset function when appropriately controlled.
Data Source
AI summary
Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal.