3D Memory Control Logic Stacking for Higher Density NAND
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Solution Overview
Problem
Conventional microelectronic device designs face challenges in increasing memory density and performance due to processing conditions and the complexity of control logic devices, which often consume more space and hinder miniaturization and performance improvements.
Innovation Solution
The approach involves forming a microelectronic device with a first microelectronic device structure containing a memory array region and associated circuitry, and a second microelectronic device structure with high-performance control logic devices, allowing for separate processing conditions and reduced thermal budgets, enabling smaller die sizes and increased parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control logic devices are integrated within the memory device structure, then control functionality is provided, but the control logic devices consume excessive die area and hinder memory density improvement
Solution Approach 1:
The patent divides the microelectronic device into separate structures: a first microelectronic device structure containing the memory array region, and a second microelectronic device structure containing the control logic devices. This segmentation allows each component to be optimized independently and reduces the die area consumed by control logic within the memory device structure.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration to a three-dimensional stacked architecture where the second microelectronic device structure (control logic) is positioned vertically over the first microelectronic device structure (memory array). This dimensional change enables higher density by utilizing vertical space rather than horizontal footprint.
2Manufacturing precision
If processing conditions are optimized for memory array formation, then memory structure quality is improved, but control logic device performance is limited by thermal budget constraints
Solution Approach 1:
The patent separates the processing of memory array and control logic devices into distinct stages and structures. The memory array is formed first under optimized processing conditions, then the control logic devices are formed separately in the second structure, allowing each to receive tailored processing conditions appropriate to its specific requirements without compromising the other.
Solution Approach 2:
The memory array structure is formed first as a preliminary step, establishing a foundation that can then support the subsequent formation of control logic devices. This sequential approach allows the memory array to be optimized under its specific processing conditions before the control logic devices are added, ensuring both components achieve their respective performance targets.
3Adaptability or versatility
If control logic devices are placed within the memory device structure, then integration is achieved, but the horizontal footprint increases and device miniaturization is impeded
Solution Approach 1:
The patent moves the control logic devices from a horizontal planar arrangement to a vertical stacked configuration. The second microelectronic device structure containing control logic devices is positioned vertically over the first microelectronic device structure, transforming the layout from two-dimensional to three-dimensional and thereby reducing the horizontal footprint while maintaining high integration.
Solution Approach 2:
The patent implements a nested configuration where the second microelectronic device structure (control logic) is effectively nested over the first microelectronic device structure (memory array). This nesting arrangement allows both components to coexist in a compact vertical stack, achieving high integration without increasing horizontal footprint.
Data Source
AI summary
A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.