3D Memory Array and Logic Stacking Under Thermal Budget Limits
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing memory density and performance while dealing with thermal budget constraints and undesirable deformations during the formation of control logic devices and memory arrays, which limits the reduction of device size and improvement of operational speed and power efficiency.
Innovation Solution
The solution involves forming a microelectronic device structure by attaching a control logic region to a memory array region, where the memory array region is built over a carrier structure, allowing for separate processing of control logic devices and memory cells without thermal budget limitations, and forming source structures over the memory array to enhance interconnectivity and reduce vertical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control logic devices are formed together with memory arrays under thermal budget constraints, then manufacturing process simplicity is maintained, but device performance and miniaturization are limited
Solution Approach 1:
The patent divides the microelectronic device into separate regions: a control logic region and a memory array region. These regions are formed independently with different processing conditions, allowing each to be optimized separately. The control logic devices can undergo higher temperature processing while the memory array uses lower temperature processes, resolving the contradiction between manufacturing simplicity and device performance.
2Device complexity
If control logic devices are formed together with memory arrays, then manufacturing complexity is reduced, but device size reduction is impeded
Solution Approach 1:
By segmenting the device into control logic region and memory array region that can be formed independently, the patent enables separate optimization of each region's dimensions. This allows for greater miniaturization of the overall device while maintaining the necessary functional components, as each region can be scaled independently based on its specific requirements.
3Quantity of substance
If conventional vertical memory array architectures are used, then memory density is increased, but control logic device performance is limited by processing conditions
Solution Approach 1:
The patent separates the control logic devices from the memory array structure, allowing the memory array to maintain its high-density vertical architecture while the control logic region can be optimized independently. This segmentation removes the constraint where memory array processing conditions limited control logic performance, enabling both high memory density and high control logic performance to coexist.
Solution Approach 2:
Different regions of the device are given different local properties and processing conditions. The control logic region receives processing optimized for transistor performance while the memory array region receives processing optimized for high-density storage. This local quality differentiation resolves the contradiction between memory density and control logic performance.
4Reliability
If processing conditions are optimized for memory array formation, then memory cell performance is improved, but control logic device configurations are limited
Solution Approach 1:
By forming the control logic region and memory array region separately, the patent allows each region to have its processing conditions independently optimized. The memory array can use processing conditions specifically tailored for high-performance memory cells, while the control logic region can explore a broader range of device configurations and materials without being constrained by memory array requirements.
Data Source
AI summary
A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.