In-Memory Logic Cell Architecture for Weight-Bit Computation
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Solution Overview
Problem
Existing memory devices are limited in their ability to perform logic operations efficiently, as they primarily focus on data storage without effectively utilizing input bits and weight bits for logic operations, leading to restricted functionality.
Innovation Solution
The memory device incorporates memory cells with switches and capacitors that utilize input bits and weight bits to perform logic operations such as AND, OR, NAND, NOR, XOR, and XNOR by generating current signals based on voltage levels, and includes resistors to manage current levels, enabling more complex logic operations and similarity searches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices are designed for simple data storage, then storage reliability is improved, but functional versatility deteriorates
Solution Approach 1:
The memory device is designed to perform multiple functions: it can store data bits and simultaneously perform logic operations (AND, OR, NAND, NOR, XOR, XNOR) and similarity searches. The memory cell structure with switches and storage nodes enables both storage and computation functions within the same device, eliminating the need for separate storage and processing units.
Solution Approach 2:
The patent combines storage functionality and logic operation functionality into a single integrated memory device. The memory cells are configured to both store weight bits and input bits, and to perform logic operations on these bits to generate output signals, merging what were traditionally separate functions into one unified system.
2Device complexity
If memory devices perform only data storage, then device complexity is reduced, but operational functionality deteriorates
Solution Approach 1:
The memory device performs multiple operations including data storage, logic operations (AND, OR, NAND, NOR, XOR, XNOR), and similarity searches using the same hardware structure, providing universal functionality without requiring separate dedicated circuits for each operation.
Solution Approach 2:
Weight bits are pre-stored in the memory cells before logic operations are performed. This preliminary storage of weight bits enables the memory device to quickly perform logic operations and similarity searches by comparing input bits against the pre-stored weight bits, reducing operational complexity.
3Ease of manufacture
If memory cells use traditional storage architecture, then manufacturing simplicity is improved, but logic operation capability deteriorates
Solution Approach 1:
The memory cell is designed with switches and storage nodes that can be manufactured using standard memory fabrication processes, yet these same components enable both data storage and logic operations, achieving multi-functionality without requiring complex manufacturing steps.
Solution Approach 2:
The memory cell utilizes voltage level changes to represent logic values and perform operations. By changing the voltage parameters applied to the switches and storage nodes, the same physical structure can perform different logic operations, enabling versatility through parameter control rather than structural complexity.
Data Source
AI summary
A memory device includes a first memory cell performing a logic operation. The first memory cell includes first and second switches. The first switch writes a first weight bit into a first storage node. The second switch generates a first current signal according to the first weight bit and a first input bit. The second switch receives a first bit line signal carrying the first input bit and a first word line signal. A control terminal of the second switch is coupled to the first storage node. When the first input bit has a first logic value, the first bit line signal and the first word line signal has a first voltage level. When the first input bit has a second logic value, the first bit line signal has a second voltage level smaller than the first voltage level.